Senior Staff Engineer, Multi-die 3DIC - Santa Clara, CA, United States
$127,630 - $191,200 USD yearly
Originally posted 22 September 2026 by the employer.
About the role
The position focuses on methodologies for Multi-die and Power to address the needs of various Marvell Business Units.
What you'll do
- Develop and maintain next-gen CAD Flows & Methodologies for Multi-die and Power.
- Contribute to the deployment, support, and regressions of these flows.
- Collaborate with Infrastructure teams for optimal flow integration.
- Drive weekly engagement with external partners and internal customers to track product requirements and EDA tool development.
What you'll need
- BS/MS in EE/CS with 7+ years of hands-on experience in physical design and flow development in an ASIC rtl-to-gds environment.
- Strong proficiency in TCL and python scripting for CAD flow development.
- Experience with 2.5D/3D/3.5D die-stacking, floor planning, SOIC hybrid bonding.
- Experience with inter-die extraction and multi-die analysis (IR, STA, thermal).
- Experience with advanced packaging technologies: CoWoS, EMIB, PIVR, COUPE.
- Experience with interposer routing for silicon & fanout, SI/PI analysis.
- Experience with industry design tools including 3DIC Compiler, Integrity 3DIC, Fusion Compiler, Innovus.
Skills: Multi-die 3DIC, 2.5D/3D/3.5D die-stacking, SOIC hybrid bonding, Advanced packaging technologies, Interposer routing, SI/PI analysis
This role has been open 0 days — well below the 84-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
|
Median days open
84 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (39 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 39 |
| Median days open | 20 d | 84 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: Multi-die 3DIC, 2.5D/3D/3.5D die-stacking, SOIC hybrid bonding, Advanced packaging technologies, Interposer routing, SI/PI analysis
Who's hiring in this category
- Qualcomm · 5 open roles · median 84 d
- Marvell Technology (this employer) · 4 open roles · median 75 d
- Micron Technology · 4 open roles · median 131 d
- NVIDIA · 4 open roles · median 43 d
- AMD · 3 open roles · median 46 d
- Applied Materials · 2 open roles · median 72 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 20 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.