Senior Staff Engineer, HPC & EDA Design Infrastructure - San Jose, California, United States
$189,000 - $301,000 USD yearly
Originally posted 7 August 2026 by the employer.
About the role
We are seeking a Senior Staff Engineer to build and optimize the EDA design environment and large-scale compute infrastructure that supports semiconductor design organizations. This role designs and standardizes shared design environments and infrastructure across multiple design organizations, driving engineering productivity and cost efficiency.
What you'll do
- Define standard processes and guidelines for design flow onboarding, tool qualification, and version control; set up, deploy, operate, and provide technical support for EDA tool environments.
- Lead EDA vendor relationship management, contract negotiations, and renewals; determine appropriate license quantities through utilization monitoring and demand forecasting; optimize cost by identifying and reallocating idle licenses; own the architecture and operation of license servers.
- Define the EDA design environment and infrastructure roadmap and prioritize requirements from design organizations.
- Design LSF compute farm cluster architecture, define queue and resource policies, tune job scheduling, drive utilization-based performance improvements, and plan capacity.
- Build, operate, and establish the user support model for the user login environment (Exceed TurboX, ETX).
- Own governance, upgrades, and migrations for Engineering collaboration and DevOps platforms (Jira, Confluence).
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 15+ years in CAD/CAE, EDA infrastructure, design infrastructure, or HPC for semiconductor design.
- Experience building and operating EDA design environments and providing technical support to design organizations.
- Experience with EDA license contract management, license server operations, and utilization-based capacity optimization.
- Experience building and operating large-scale compute farms with IBM LSF (or SLURM, Grid Engine) and tuning job scheduling.
Skills: EDA design environment, license management, LSF compute farm, Cadence Synopsys Siemens, design automation
This role has been open 70 days — below the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
675
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (675 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 675 |
| Open roles in the wider Physical Implementation family | 3 | 1442 · 110 employers |
| Median days open | 79 d | 73 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: EDA design environment, license management, LSF compute farm, Cadence Synopsys Siemens, design automation
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 169 d
- Synopsys · 63 open roles · median 38 d
- Micron Technology · 44 open roles · median 46 d
- Qualcomm · 36 open roles · median 74 d
- GlobalFoundries · 33 open roles · median 37 d
- Keysight Technologies · 32 open roles · median 71 d
How we counted: 675 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.