Senior Staff Engineer, Digital Verification and Methodology - Lexington, KY, United States
$121,840 - $182,760 USD yearly
Originally posted 1 October 2026 by the employer.
About the role
This role involves leading functional verification for advanced integrated circuits and scaling reusable methodologies across global development sites.
What you'll do
- Lead end-to-end verification strategy from requirements analysis through sign-off.
- Architect reusable SystemVerilog UVM environments and scalable object-oriented testbenches.
- Implement constrained-random and assertion-based verification with robust functional coverage.
- Drive metric-driven coverage closure and establish clear quality criteria.
- Translate specifications and microarchitecture into tests, checkers, coverage models, and sign-off evidence.
- Improve verification methodologies, automation, and tool flows across projects and development sites.
What you'll need
- Bachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field.
- 5+ years in ASIC, SoC, or FPGA functional verification with ownership of complex block, subsystem, or chip-level deliverables.
- Expert proficiency in SystemVerilog, UVM, object-oriented testbench architecture, constrained-random verification, functional coverage, and assertion-based verification.
- Ability to translate specifications and microarchitecture into verification plans, environments, tests, checkers, coverage models, and sign-off evidence.
- Written and spoken English at C1 level.
Nice to have
- Experience with RTL design and digital architecture.
- Exposure to Ethernet or complex protocols.
- Security verification for cryptographic accelerators or secure subsystems.
- Power-aware verification using UPF.
- Practical use of AI or machine learning and AI-enabled EDA tools.
- Strong debugging skills with a major simulation and debug toolchain and proficiency in Linux development and scripting or programming with Python, Tcl, Bash, C, or C++ for automation.
Skills: SystemVerilog, UVM, constrained-random verification, functional coverage, assertion-based verification
This role has been open 14 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 40 | 1195 |
| Open roles in the wider Digital Design & Verification family | 93 | 3204 · 115 employers |
| Median days open | 62 d | 64 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: SystemVerilog, UVM, constrained-random verification, functional coverage, assertion-based verification
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.