$164,000 - $246,000 USD yearly
Originally posted 9 September 2026 by the employer.
About the role
This role defines the future of silicon Diagnostics, AI, and yield intelligence within Qualcomm's Yield Architecture and Engineering organization. You will operate as a research and development leader with a specialty in Diagnostics, using technical vision, architecture, influence, governance, and mentoring to shape capabilities across organizational boundaries.
What you'll do
- Define and evolve the architecture for Qualcomm's scan, memory, and emerging diagnostic capabilities.
- Provide technical leadership for reliable, scalable, high-volume, production-quality scan and memory diagnostics across Qualcomm's product portfolio.
- Drive AI, agentic workflows, analytics, and automation across Diagnostics and adjacent yield workflows.
- Connect Diagnostics, Failure Analysis, DFT, Product Engineering, Test Engineering, Design, manufacturing data, and yield learning.
- Lead problems where requirements, ownership, data, or solution paths are unclear, framing the challenge and establishing a credible path forward.
- Build a technical community across Diagnostics, AI, Automation, and partner disciplines, promoting reusable solutions and shared methods.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- Deep understanding of diagnostic concepts, methods, workflows, data, or infrastructure.
- Ability to understand complex systems across lifecycle and organizational boundaries, and design for reuse, learning, scale, and evolution.
- Experience defining strategy, roadmaps, and architectures and leading major initiatives spanning multiple teams or functions.
- Ability to build alignment, resolve unclear ownership, influence decisions, and sustain execution without relying on direct reporting authority.
- Experience with project plans, architecture reviews, roadmaps, metrics, risk management, decision frameworks, ownership models, and escalation paths.
Nice to have
- Bachelor's or advanced degree in Electrical Engineering, Computer Engineering, Computer Science, Data Science, or a related field.
- 12 years of semiconductor engineering experience, including significant work in ATPG or memory diagnostics, DFT, silicon debug, product or test engineering, yield analysis, Failure Analysis, Design for Debug, Design for Yield, or post-silicon engineering.
- Experience architecting or scaling automation, analytics, machine learning, generative AI, agentic systems, data platforms, or intelligent engineering workflows in a technically complex domain.
- Ability to learn unfamiliar technologies quickly, identify implications for Diagnostics and yield learning, and formulate research or architecture directions.
- Ability to understand stakeholders, dependencies, decision rights, operating mechanisms, capability gaps, and competing priorities, and to take responsibility for shared outcomes.
- Success framing and solving problems where requirements, approaches, data, ownership, or success criteria were initially unclear.
- Strong partnership across Design, DFT, Product Engineering, Test Engineering, Failure Analysis, Yield Engineering, software, data, Automation, or AI.
- Experience leading across geographic, functional, and cultural boundaries and developing technical ownership in distributed teams.
- Ability to convert innovative ideas into working capabilities, scalable methods, or sustained practices.
- Ability to connect technical communities, encourage knowledge exchange, and build shared purpose across evolving environments.
Skills: silicon Diagnostics, scan, memory diagnostics, Design for Debug, Design for Yield, AI accelerator
This role has been open 35 days — well below the 56-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
250
|
Median days open
56 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (250 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 250 |
| Open roles in the wider Digital Design & Verification family | 377 | 3189 · 115 employers |
| Median days open | 101 d | 56 d (+45 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: silicon Diagnostics, scan, memory diagnostics, Design for Debug, Design for Yield, AI accelerator
Who's hiring in this category
- AMD · 40 open roles · median 41 d
- NVIDIA · 25 open roles · median 41 d
- Qualcomm (this employer) · 24 open roles · median 101 d
- NXP Semiconductors · 18 open roles · median 63 d
- Synopsys · 13 open roles · median 23 d
- Micron Technology · 11 open roles · median 54 d
How we counted: 250 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.