Senior Staff Digital Design Engineer
Originally posted 18 September 2026 by the employer — open 0 days.
This role focuses on developing high performance connectivity silicon that underpins AI scale data centers for hyperscalers.
About the role
This role involves the design and implementation of complex digital integrated circuits. You will contribute to the development of high performance connectivity silicon that underpins AI scale data centers for hyperscalers.
What you'll do
- Collaborate with systems and architecture teams to define SoC-level specifications.
- Translate high-level product and protocol requirements into detailed micro-architecture specifications for complex subsystems, high-speed datapaths, DSP pipelines, and IP blocks.
- Own RTL development for assigned blocks, delivering high-quality, synthesizable SystemVerilog RTL that meets functionality, performance, and power targets.
- Implement and drive the full ASIC front-end design flow, including lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness.
- Partner with STA and PNR teams to support timing closure, floorplanning, congestion analysis, and design optimizations across advanced process nodes.
- Drive post-silicon bring-up and debug, collaborating with lab and systems teams to validate functionality, characterize performance, and resolve complex issues across datapath, DSP, and protocol layers.
What you'll need
- Extensive experience in digital ASIC design, including micro-architecture development, RTL implementation, and integration of complex logic blocks.
- 3-10+ years of industry experience working on large-scale ASICs for networking, data-center connectivity, or high-bandwidth compute architectures.
- Strong background in high-performance DSP and high-speed datapath design, including pipelined arithmetic units, algorithm-driven hardware implementation, packet processing engines, memory subsystems, and large-scale control/state machines.
- Familiarity with Ethernet protocols and networking standards, including MAC, PCS framing, flow control, and packet-level behaviors.
- Proficiency with front-end design flows, including lint, CDC/RDC, synthesis, STA, and power/performance optimization.
- Familiarity with advanced process nodes (5nm, 3nm, or similar) and their implications for timing, power, and signal integrity.
Nice to have
- Advanced high-speed DSP algorithm implementation, including adaptive equalization (FFE, DFE, CTLE), channel estimation, and high-throughput filtering architectures.
- Experience with FEC architectures such as LDPC, RS, BCH, or other high-speed coding/decoding schemes used in networking and optical interconnects.
- Previous PHY design experience, including PMA-level DSP pipelines, equalization blocks, clock recovery, and SerDes-adjacent logic.
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
929
|
Median days open
62 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (929 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 929 |
| Open roles in the wider Digital Design & Verification family | 24 | 3006 · 114 employers |
| Median days open | 63 d | 62 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Who's hiring in this category
- Qualcomm · 136 open roles · median 58 d
- AMD · 60 open roles · median 68 d
- Synopsys · 56 open roles · median 30 d
- NXP Semiconductors · 52 open roles · median 67 d
- NVIDIA · 48 open roles · median 46 d
- Analog Devices · 38 open roles · median 76 d
How we counted: 929 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.