Senior Staff Design Verification Engineer - Bangalore, Karnataka, India
Originally posted 28 September 2026 by the employer.
About the role
This role involves delivering high-quality verification solutions for complex System-on-Chip (SoC) products within Smart Analog and Sensors.
What you'll do
- Develop and maintain advanced UVM-based verification environments for complex SoC and subsystem-level designs.
- Define comprehensive verification plans based on architecture and design specifications.
- Create reusable verification infrastructure, agents, scoreboards, monitors, and checkers.
- Develop constrained-random and directed test scenarios to validate functionality and corner-case behavior.
- Verify processor, memory, interconnect, sensor, and peripheral subsystems at both block and SoC levels.
- Analyze code coverage, functional coverage, and assertion coverage to ensure verification completeness.
- Debug RTL, testbench, integration, and simulation failures and drive resolution with cross-functional design teams.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, or related discipline.
- Minimum 8 years of industry experience in digital design verification or SoC verification.
- Strong expertise in SystemVerilog and UVM-based verification methodologies.
- Hands-on experience with constrained-random verification, assertions (SVA), coverage-driven verification, and debugging.
- Experience verifying processors, memory subsystems, interconnects, and complex SoC architectures.
- Proficiency in scripting languages such as Python, Perl, Tcl, or Shell for automation.
Nice to have
- Master's degree or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
- Knowledge of formal verification techniques and low-power verification methodologies.
- Experience with emulation, FPGA prototyping, or hardware/software co-verification.
- Familiarity with ARM-based SoC architectures and industry-standard bus protocols such as AXI, AHB, APB, PCIe, or Ethernet.
- Experience in verification automation frameworks, CI/CD integration, and regression infrastructure.
- Demonstrated technical leadership and mentoring experience.
Skills: UVM-based verification, SystemVerilog, constrained-random, coverage closure, SoC verification
This role has been open 18 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1195 |
| Open roles in the wider Digital Design & Verification family | 41 | 3204 · 115 employers |
| Median days open | 115 d | 64 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM-based verification, SystemVerilog, constrained-random, coverage closure, SoC verification
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.