Physical Design & EDA
Originally posted 28 September 2026 by the employer.
About the role
You will define the organization's design methodology and workflow.
What you'll do
- Develop and maintain automated P&R flows for various Business Units.
- Implement Power Grid for various tech nodes, meeting IR drop requirements.
- Deploy and support these design flows.
- Collaborate on optimal integration within the overall CAD platform.
- Interface with EDA vendors for tool usage optimization.
What you'll need
- 4+ years of professional experience in Computer Science, Electrical Engineering, or related fields.
- 2+ years of recent experience with Cadence Innovus.
- Proven experience with advanced nodes 5nm or below tape out, familiar with Finfet, Dual Patterning, and ULV challenges.
- Experience with Power Grid implementation and IR drop analysis.
- Solid understanding of Timing closure, Floorplanning, Routability, Power Grid design and validation, Clock synthesis schemes, SI, EM/IR, complex DRC rules, Power intent, Multiple power domains, high speed and low power implementation techniques.
- Proficiency in Tcl scripting for flow development.
Nice to have
- Ability to run Gate-to-gate equivalence checking.
- Ability to run Parasitic Extraction.
- Ability to run STA.
- Ability to run Physical Verification (at least DRC).
- Knowledge of Early Rail Analysis, EM/IR flow.
- Experience with implementation exploration methods.
- Experience with EDA tool benchmarks.
Market context
This role has been open 1 day — well below the 82-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
692
|
Median days open
82 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (692 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 692 |
| Open roles in the wider Physical Implementation family | 17 | 1419 · 109 employers |
| Median days open | 83 d | 82 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 161 d
- Synopsys · 53 open roles · median 47 d
- NVIDIA · 42 open roles · median 74 d
- Micron Technology · 41 open roles · median 109 d
- Qualcomm · 35 open roles · median 68 d
- GlobalFoundries · 27 open roles · median 49 d
How we counted: 692 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.