Senior Staff ASIC Verification Engineer-18604
Originally posted 3 September 2026 by the employer.
Work on DDR PHY and memory subsystem IP blocks.
About the role
This Senior Staff ASIC Verification Engineer will define and track verification test plans for DDR PHY and memory subsystem IP blocks, translating architecture specifications into executable verification strategies.
What you'll do
- Define and track verification test plans for DDR PHY and memory subsystem IP blocks.
- Design and write constrained-random System Verilog testbenches using UVM.
- Write System Verilog assertions and functional coverage models.
- Debug RTL and gate-level simulation failures with design engineers.
- Perform code coverage analysis and drive coverage closure.
- Mentor verification engineers in test benches, debugging strategies, and verification plans.
What you'll need
- Bachelor’s degree in electrical engineering or computer engineering with 8+ years of hands-on ASIC verification experience.
- Deep proficiency in UVM methodology and System Verilog.
- Strong understanding of DDR memory architecture and DDR PHY design, including timing, training, and calibration flows.
- Working knowledge of DFI protocol, memory controllers, or memory subsystem integration.
- Solid scripting ability in Perl or Python for automation, result parsing, and flow development.
- Proven debugging skills across RTL and gate-level simulations.
Nice to have
- Experience with AI-assisted verification tools and workflows.
Skills: UVM, System Verilog, DDR memory architecture, DDR PHY, functional coverage
This role has been open 40 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 63 | 1192 |
| Open roles in the wider Digital Design & Verification family | 167 | 3189 · 115 employers |
| Median days open | 30 d | 65 d (−35 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM, System Verilog, DDR memory architecture, DDR PHY, functional coverage
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys (this employer) · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.