Senior STA Engineer - Ahmedabad, Gujarat, India
Originally posted 11 September 2026 by the employer — open 4 days.
This role focuses on CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
About the role
This Senior STA Engineer role involves owning Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. You will work on CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
What you'll do
- Own STA and timing signoff activities from synthesis through physical design and tape-out.
- Perform MCMM/MMMC timing analysis across all functional and test modes.
- Develop, review, and validate SDC constraints, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.
- Perform detailed clock tree and clock timing analysis, including skew, latency, uncertainty, jitter, and clock reconvergence.
- Drive timing closure in collaboration with RTL, synthesis, physical design, and ECO teams.
- Develop and maintain Tcl/Python automation for STA analysis, report generation, and flow optimization.
What you'll need
- 6+ years of experience in Static Timing Analysis and timing closure.
- Hands-on experience with Synopsys PrimeTime, Cadence Tempus, or equivalent STA tools.
- Excellent knowledge of SDC constraints and timing exceptions.
- Strong understanding of ASIC/SoC design, synthesis, physical design, and signoff flows.
- Expertise in MCMM/MMMC analysis.
- Good understanding of OCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing.
- Strong knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence.
- Proficiency in Tcl scripting; Python/Perl scripting is an advantage.
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.
Skills: Static Timing Analysis, timing signoff, ASIC/SoC designs, SDC constraints, Synopsys PrimeTime
This role has been open 4 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
611
|
Median days open
59 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (611 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 611 |
| Open roles in the wider Physical Implementation family | 25 | 1411 · 108 employers |
| Median days open | 96 d | 59 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Static Timing Analysis, timing signoff, ASIC/SoC designs, SDC constraints, Synopsys PrimeTime
Who's hiring in this category
- Qualcomm · 100 open roles · median 39 d
- Broadcom · 39 open roles · median 64 d
- NVIDIA · 37 open roles · median 39 d
- AMD · 31 open roles · median 50 d
- Synopsys · 27 open roles · median 67 d
- Renesas Electronics · 24 open roles · median 49 d
How we counted: 611 open Physical Design (Physical Design) roles from 76 employers tracked in the SemiconductorJobs index, counted 15 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.