$129,450 - $215,740 USD yearly
Originally posted 28 August 2026 by the employer.
Advance the core architecture of a semiconductor design platform optimized for 3D Heterogeneous Integration.
About the role
As a Senior Software Engineer, you will advance the core architecture of a semiconductor design platform, expanding data representations, system-level APIs, and high-performance execution engines. This role focuses on complex 3D Heterogeneous Integration (3DHI) and programmatic workflows, partnering with domain experts across physical layout, schematic verification, and simulation.
What you'll do
- Drive technical decisions, platform design, and architectural evolution for core packaging engines.
- Design scalable APIs, data-exchange layers, and execution pipelines for code-first design flows.
- Architect extensible, decoupled integration interfaces for interoperability with internal solvers and third-party simulation tools.
- Optimize high-throughput runtime engines for automated design-space exploration and batch execution.
- Develop robust validation loops and constraint-checking mechanisms to ensure designs satisfy physical and manufacturability requirements.
- Partner with domain specialists, systems leads, and engineering teams to establish design standards and review complex codebases.
What you'll need
- Bachelor’s, Master’s, or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering or related technical field.
- 8+ years of software development experience, including 2+ years in software architecture.
- Strong expertise in C++ and/or Rust.
- Demonstrated experience architecting complex data structures for large-scale engineering applications.
- Strong background in building low-latency, high-throughput backend services, or multi-threaded/concurrent data engines.
- Demonstrated ability to drive consensus on complex technical design trade-offs, author clear architecture specifications, and guide large feature initiatives.
- Deep commitment to software quality, including automated test frameworks, deterministic build environments, CI/CD pipelines, and rigorous code-review practices.
Nice to have
- Strong proficiency in Python, with experience in C++/Rust integration.
- Experience designing validation frameworks, rule-checking engines, and telemetry to track state changes and catch constraint violations early.
- Familiarity with programmatic interaction patterns or multi-agent execution frameworks.
- Familiarity with electronic design and packaging abstractions, such as schematic connectivity, physical layout hierarchies, netlisting, or multi-die 2.5D/3D packaging concepts.
Skills: semiconductor design platform, 3D Heterogeneous Integration, physical layout, schematic verification, multi-physics verification
This role has been open 47 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 688 |
| Open roles in the wider Physical Implementation family | 38 | 1463 · 108 employers |
| Median days open | 89 d | 78 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: semiconductor design platform, 3D Heterogeneous Integration, physical layout, schematic verification, multi-physics verification
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.