Senior Software Engineer – AI for RTL Design & Formal Verification - San Jose, California, United States
$160,500 - $200,000 USD yearly
Originally posted 31 August 2026 by the employer. Relisted by the employer on 21 October 2026.
About the role
As a member of Astera Labs' AppliedAI organization, you will develop and deploy AI-driven agents that support RTL and physical design, static analysis, and formal verification workflows. This role sits at the intersection of digital design, verification, and AI tooling to apply LLMs and agentic systems to chip design challenges.
What you'll do
- Design, develop, and deploy AI applications using LLMs, agentic frameworks, and related technologies to support RTL, physical and analog design, static/lint checking, and formal verification flows. - Build infrastructure to deploy LLM-powered engineering assistants and multi-turn dialogue systems to aid in debugging and coverage closure. - Develop agentic AI solutions for tasks such as RTL rule and lint checking, RTL optimization, bug triage, formal proof convergence, and static verification report analysis. - Fine-tune and integrate AI solutions with existing CAD/EDA flows. - Build and maintain design databases and dashboards combining agentic and deterministic retrieval to surface engineering data. - Collaborate with RTL design, DV, formal verification, and CAD/EDA teams to translate hardware workflow requirements into AI-assisted tooling.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience. - 4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies. - Proficiency in Python for rapid prototyping, with strong fundamentals in data structures, algorithms, and software engineering practices. - Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases. - Familiarity with RTL design languages (Verilog/SystemVerilog) and formal/static verification tools (e.g., JasperGold, VC Formal, or similar). - Proactive problem-solving skills and the ability to operate effectively in an ambiguous technical environment.
Nice to have
- Direct experience applying AI/ML techniques to EDA or CAD flow problems. - Proficiency in modern software engineering practices, including version control, testing, and CI/CD. - Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools. - A track record of combining AI/ML and hardware design domains into novel engineering solutions.
This role has been open 51 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1051
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1051 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 32 | 1051 |
| Open roles in the wider Digital Design & Verification family | 64 | 3283 · 116 employers |
| Median days open | 39 d | 62 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 150 open roles · median 57 d
- Synopsys · 84 open roles · median 35 d
- AMD · 72 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 89 d
- NVIDIA · 40 open roles · median 62 d
How we counted: 1051 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.