Senior SoC Power Analysis & Optimization Engineer - Mountain View, CA, United States

Originally posted 22 July 2026 by the employer.

About the role

The Senior SoC Power Analysis & Optimization Engineer develops power estimation methodologies and conducts power analysis and optimization for AI accelerator SoCs across compute, memory, and high-speed connectivity subsystems.

What you'll do

- Develop and maintain power estimation methodologies and calibrate energy models for early architectural exploration and power target definition. - Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems. - Analyze AI workloads and application use cases to identify opportunities for dynamic and static power reduction. - Drive power optimization across compute, memory, interconnect, PCIe, HBM, clock/reset, and other SoC subsystems. - Collaborate with architects, RTL designers, and physical design teams to evaluate implementation trade-offs and implement power-efficient microarchitecture. - Develop automation, scripts, dashboards, and heuristics to support power analysis and root-cause investigation.

What you'll need

- BS or MS in Electrical Engineering, Computer Engineering, or a related field. - 8+ years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design. - Strong understanding of computer architecture and SoC design. - Experience with ASIC low-power design techniques. - Experience performing RTL and gate-level power analysis. - Experience with Python, Perl, or similar scripting languages.

Nice to have

- RTL development experience using Verilog/SystemVerilog. - Experience with clock distribution, multiple clock domains, clock gating, and power-aware RTL design. - Experience with synthesis, static timing analysis, place-and-route, and implementation flows. - Experience developing power models, budgeting methodologies, and projection flows. - Experience analyzing large power datasets using scripting and data analytics. - Experience correlating pre-silicon power estimates with silicon measurements. - Experience with AI workload characterization and power-performance analysis.

Skills: SoC power analysis, AI accelerator, low-power design, RTL power analysis, gate-level power analysis, power optimization