Senior SOC Physical Design Engineer
$131,175 - $173,400 USD yearly
Originally posted 15 September 2026 by the employer — open 5 days.
About the role
This individual plans and performs physical design flow responsibilities for system-on-chip (SoC) products. The role focuses on high-speed DDR, graphics, and physical verification flows, including target power utilization and optimization.
What you'll do
- Independently plan and perform moderately-defined physical design flow tasks.
- Execute Floor Planning, Clock Tree Synthesis, Place and Route, PDN, and Timing analysis and closure.
- Conduct physical verification checks such as LVS, DRC, design-for-manufacturing, and design-for-yield at chip and block levels.
- Provide schedules and support cross-functional engineering efforts for signoff closure for tapeout.
- Contribute to design reviews and project meetings.
What you'll need
- Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
- Experience with Physical Design Flow for high-speed DDR.
- Experience with graphics physical design flows.
- Expertise in Floor Planning.
- Expertise in Clock Tree Synthesis.
- Expertise in Place and Route.
- Expertise in PDN.
- Expertise in Timing analysis and closure.
- Experience with LVS.
- Experience with DRC.
- Experience with design-for-manufacturing.
- Experience with design-for-yield.
Skills: Floor Planning, Clock Tree Synthesis, Place and Route, Timing analysis, LVS, DRC
This role has been open 4 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
604
|
Median days open
59 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (604 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 108 | 604 |
| Open roles in the wider Physical Implementation family | 148 | 1373 · 107 employers |
| Median days open | 42 d | 59 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Floor Planning, Clock Tree Synthesis, Place and Route, Timing analysis, LVS, DRC
Who's hiring in this category
- Qualcomm (this employer) · 108 open roles · median 42 d
- NVIDIA · 39 open roles · median 44 d
- Broadcom · 38 open roles · median 69 d
- AMD · 35 open roles · median 39 d
- Synopsys · 27 open roles · median 58 d
- Renesas Electronics · 25 open roles · median 46 d
How we counted: 604 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.