Senior Silicon Validation Methodology Engineer - Shanghai, China
Originally posted 6 October 2026 by the employer.
Define and implement silicon validation methodology for Clocking and High-Speed I/O.
About the role
As a Senior Silicon Validation Methodology Engineer, you will own the clocking and High-Speed I/O functional validation methodology for products across GPU, SOC, and CPU.
What you'll do
- Own the definition and first-use of clocking and HSIO functional validation methodology from specification through silicon bring-up.
- Define testing requirements, including coverage bounds, timing vs. power, signal integrity vs. performance, and create executable test content.
- Drive cross-functional team collaboration to ensure robust methodology orchestration and alignment with validation design requirements.
- Drive continuous improvement in validation methodologies by creating and standardizing automated tools, scripts, and metrics.
- Debug silicon HSIO and clocking issues, deconstructing failures into reusable validation and corrective approaches.
What you'll need
- Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
- 8+ years of hands-on silicon validation methodology experience with deep understanding of HSIO and Clocking architecture, design, and validation.
- Experience with SerDes, protocol, functional and electrical validation, SI/PI, and power-aware trade-offs.
- Experience in at least one of PCIe, CXL, USB, UFS, MGBE, or chip-to-chip / die-to-die interconnects.
- Demonstrated ability to set validation strategy under trade-offs such as functionality vs. power, signal integrity vs. performance, and coverage vs. test time.
Skills: silicon validation, clocking, High-Speed I/O, SerDes, PCIe
This role has been open 0 days — well below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
392
|
Median days open
41 d
|
Median salary
$175k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (392 roles · 64 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 392 |
| Open roles in the wider Silicon Validation & Test family | 97 | 2207 · 110 employers |
| Median days open | 26 d | 41 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $175k |
Skills observed across this category: silicon validation, clocking, High-Speed I/O, SerDes, PCIe
Who's hiring in this category
- AMD · 57 open roles · median 51 d
- Micron Technology · 42 open roles · median 33 d
- Qualcomm · 31 open roles · median 27 d
- NVIDIA (this employer) · 21 open roles · median 30 d
- Graphcore · 19 open roles · median 108 d
- Microchip Technology · 19 open roles · median 65 d
How we counted: 392 open Post-Silicon Validation (Silicon Validation) roles from 64 employers tracked in the SemiconductorJobs index, counted 7 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.