Senior Silicon Circuit Co-Design Engineer - CA, Santa Clara, United States
$168,000 - $264,500 USD yearly
Originally posted 15 September 2026 by the employer.
Co-design analog, digital, and mixed-signal circuits that underpin NVIDIA's safety, security, reliability, and performance enhancement features.
About the role
This role involves co-designing and validating the critical circuits that determine product trustworthiness in NVIDIA's silicon, ensuring security boundaries, failure prevention, extended silicon lifetime, and safe performance margins. The position focuses on closing the gap between design intent and silicon reality by understanding actual circuit behavior across full PVT space.
What you'll do
- Own the co-design, bring-up, and post-silicon validation of analog, digital, and mixed-signal circuits across the full PVT space.
- Build methodologies to correlate measured circuit behavior against pre-silicon predictions and quantify model divergence.
- Trace failures to their source, such as circuit marginality or process corners, and drive resolution.
- Build and own AI agents for automated test orchestration, intelligent data pipelines, and analysis flows.
- Design and own automation and analysis infrastructure for efficient execution across multiple products.
- Provide data and analysis that drives binning strategy, guard-band decisions, reliability sign-off, and design improvements.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience.
- 8+ years of hands-on silicon bring-up, frequency and power characterization, or post-silicon validation on hardware.
- Strong circuit fundamentals in analog, digital, and mixed-signal.
- Hands-on lab depth with oscilloscopes, multimeters, DAQs, spectrum analyzers, and silicon debug tools.
- Depth in product binning, PVT analysis, guard-banding, and optimization trade-offs.
- Exposure to critical path analysis, power integrity, dI/dt and PDN analysis, transistor physics, and silicon reliability and aging mechanisms.
- Scripting proficiency in Python, C/C++.
Skills: silicon bring-up, post-silicon validation, circuit fundamentals, PVT analysis, oscilloscopes
This role has been open 28 days — well below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
400
|
Median days open
41 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (400 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 400 |
| Open roles in the wider Silicon Validation & Test family | 94 | 2211 · 111 employers |
| Median days open | 21 d | 41 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Skills observed across this category: silicon bring-up, post-silicon validation, circuit fundamentals, PVT analysis, oscilloscopes
Who's hiring in this category
- AMD · 57 open roles · median 41 d
- Micron Technology · 39 open roles · median 36 d
- Qualcomm · 36 open roles · median 28 d
- NVIDIA (this employer) · 25 open roles · median 21 d
- Graphcore · 21 open roles · median 119 d
- Microchip Technology · 19 open roles · median 69 d
How we counted: 400 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.