Senior Signal Integrity Engineer – LPU Packaging - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 2 September 2026 by the employer.
About the role
As a Senior Signal Integrity Engineer on the Packaging and Systems team, you will drive high-speed SerDes channel design, simulation, and correlation for advanced packages and data center platforms. You will work across silicon, package, board, and system boundaries to develop high-speed interconnect solutions for HPC and AI applications.
What you'll do
- Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces. - Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, focusing on channel loss, discontinuities, return path behavior, and crosstalk. - Build and optimize chip-package-board co-simulation methodologies for HPC and data center systems. - Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and critical channel structures. - Perform pre-layout and post-layout signal integrity analysis, establish design guidelines, and review layouts to ensure electrical performance targets are met. - Correlate simulation results with lab measurements using TDR, VNA, and oscilloscope techniques to improve model accuracy and signoff confidence.
What you'll need
- BS, MS, or PhD in Electrical Engineering or equivalent experience. - 8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles. - Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior. - Proven experience with high-speed SerDes design and analysis for advanced packaging or large-scale system applications. - Hands-on experience with SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, or HSPICE. - Experience with S-parameters, IBIS-AMI based flows, time/frequency-domain analysis, NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end-to-end channel budgets.
Skills: high-speed SerDes, signal integrity, advanced packages, PCIe, CXL, NVLink
This role has been open 122 days — well above the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
238
|
Median days open
71 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (238 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 238 |
| Open roles in the wider Analog & Mixed-Signal family | 27 | 1441 · 106 employers |
| Median days open | 160 d | 71 d (+89 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: high-speed SerDes, signal integrity, advanced packages, PCIe, CXL, NVLink
Who's hiring in this category
- Synopsys · 35 open roles · median 37 d
- AMD · 27 open roles · median 41 d
- Qualcomm · 21 open roles · median 65 d
- Cadence Design Systems · 20 open roles · median 147 d
- Micron Technology · 15 open roles · median 38 d
- Apple · 9 open roles · median 24 d
How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.