Originally posted 12 August 2026 by the employer — open 29 days.
About the role
This role involves analyzing and optimizing signal and power integrity in complex electronic systems for Autonomous Driving products.
What you'll do
- Conduct signal integrity (SI) simulations for automotive electronic systems, optimizing high-speed interfaces like LPDDR4/5, PCIe Gen4/5, A/C/D-PHY, and Multi Giga-Bit Ethernet.
- Conduct Power integrity (PI) simulations, optimizing target impedance and AC coupling in power delivery networks.
- Collaborate with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, and EDA tools vendors to address SI/PI issues.
- Engage in joint simulation and measurement efforts with the Electrical Validation team to facilitate comprehensive validation.
- Perform root cause analysis on signal and power integrity failures and propose corrective actions.
- Generate comprehensive reports and presentations to communicate simulation findings and design strategies.
What you'll need
- Bachelor or master's degree in electrical engineering.
- At least 5 years of experience as an Integrity Engineer.
- Proven experience in signal and power integrity analysis.
- Proficiency in simulation tools such as HyperLynx, ANSYS, ADS or equivalent, including 2.5D/3D extraction.
- Strong knowledge of transmission line theory, electromagnetic principles, and PCB design best practices.
Skills: Signal Integrity, Power Integrity, LPDDR4/5, PCIe Gen4/5, HyperLynx
This role has been open 29 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Mobileye | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1317 · 100 employers |
| Median days open | 29 d | 91 d (−62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signal Integrity, Power Integrity, LPDDR4/5, PCIe Gen4/5, HyperLynx
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.