Senior Signal Integrity Engineer - Bengaluru, India
Originally posted 4 February 2026 by the employer — open 217 days.
About the role
This role involves leading board-level high-speed electrical design and validation for 1.6T DR8 (200G/lane) OSFP optical modules.
What you'll do
- Own SI/PI architecture and strategy for 1.6T DR8 OSFP modules, defining channel budgets and interface architectures.
- Lead pre- and post-layout SI/PI simulations and reviews (S-parameters, eye/PAM4 analysis, COM, crosstalk, jitter, PDN impedance).
- Define PCB stack-ups, materials, via and breakout strategies, and routing guidelines.
- Drive cross-functional technical decisions with hardware, optics, mechanical, FW, and test teams.
- Lead lab correlation and validation plans including TDR/VNA/BERT/oscilloscope measurements and de-embedding strategies.
- Provide technical leadership for SI-related debug on proto and field issues, driving root-cause analysis.
What you'll need
- 15–20 years of relevant high-speed SI/PI and board-level design experience.
- Deep expertise in very high-speed SerDes (≥56G, 100G/200G PAM4) including channel modeling, equalization strategies, jitter/crosstalk analysis.
- Extensive hands-on experience with SI/PI tools (Sigrity, ADS, HFSS, SIwave, HSPICE or equivalents) and scripting/automation.
- Proven track record bringing complex high-speed hardware or optical modules from concept through production.
- Strong lab expertise with high-bandwidth scopes, VNAs, BERTs, and TDRs, including correlation of measurements to simulations.
- Demonstrated ability to lead cross-functional design reviews and communicate complex SI/PI concepts.
Nice to have
- Direct experience with OSFP/OSFP-XD/QSFP-DD optical transceiver designs at 800G/1.6T or similar data-center interconnects.
- Knowledge of IEEE 802.3 DR8/FR8/LR8-class electrical/optical standards and relevant MSAs/OIF specifications.
- Background in EMI/EMC, mechanical and thermal considerations for pluggable modules.
- Experience managing or technically leading small SI/PI or hardware teams.
Skills: PAM4, SI/PI, channel modeling, Sigrity, TDR/VNA/BERT
This role has been open 34 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 5 | 1317 · 100 employers |
| Median days open | 34 d | 91 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PAM4, SI/PI, channel modeling, Sigrity, TDR/VNA/BERT
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.