Senior Signal and Power Integrity Engineer - Hardware - CA, Santa Clara, United States
$136,000 - $264,500 USD yearly
Originally posted 6 October 2026 by the employer.
Work on complex system design problems involving high-speed NVlink 200Gbs+, USB-4, PCIe5, GDDR6, and LP5X interfaces.
About the role
As a Senior Signal and Power Integrity Engineer, you will craft creative Signal Integrity solutions for complex system design problems. This role involves working with high-speed interfaces like NVlink 200Gbs+, USB-4, PCIe5, GDDR6, and LP5X.
What you'll do
- Craft creative Signal Integrity solutions to complex system design problems.
- Model and optimize vias, connectors, sockets, breakouts, and various system components in 3D EM tools.
- Perform system-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5, GDDR6, LP5X, and other interfaces.
- Improve SI models using data from lab measurements and/or modeling tool/methodology updates.
- Create substrate and board layout SI guidelines, review them, and perform post layout SI extractions.
- Automate simulations, gather data, and analyze/visualize results using JMP, MATLAB, or similar tools.
What you'll need
- BS/MS in Electrical Engineering or equivalent experience with 3+ years of industry experience.
- Strong technical background in applied electromagnetics, transmission line theory, and signal processing.
- SI work on one or more signaling standards like PCI express, USB, SATA, HDMI, HBM, DDR5, GDDR6, LPDDR5X.
- Hands-on use of 3-D modeling tools like ANSYS HFSS/Q3D, 2.5-D with ANSYS SIWAVE or similar, and 2D such as Ansys2D.
- Familiarity with a system level timing or loss budget including silicon, package, and board impairments.
Nice to have
- Experience in interconnect electromagnetic model design for 200Gbps systems, particularly in backplane and midplane architectures.
- Hands-on expertise in characterizing and correlating high-speed interconnects including PKG, PCB, connectors, and cable assemblies in the lab (including using VNA and probing).
- Ability to post-process and analyze interconnect measured SI data, using statistics when necessary, to assess performance at production sites.
- Knowledge of circuit design, board/package technology & design, link architecture, and timing budget methodologies.
Skills: signal integrity, power integrity, 3D EM tools, PCIe5, GDDR6
This role has been open 2 days — well below the 114-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · Serdes Highspeed
|
Open roles in category
89
|
Median days open
114 d
|
Median salary
$199k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (89 roles · 36 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 89 |
| Open roles in the wider Software, Firmware & Systems family | 966 | 6047 · 146 employers |
| Median days open | 94 d | 114 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $199k |
Skills observed across this category: signal integrity, power integrity, 3D EM tools, PCIe5, GDDR6
Who's hiring in this category
- NVIDIA (this employer) · 14 open roles · median 92 d
- Qualcomm · 10 open roles · median 183 d
- AMD · 8 open roles · median 84 d
- Keysight Technologies · 5 open roles · median 141 d
- Lumentum · 4 open roles · median 11 d
- Broadcom · 3 open roles · median 193 d
How we counted: 89 open Hardware Systems Engineering (Serdes Highspeed) roles from 36 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.