Senior Signal and Power Integrity Engineer - United States
Originally posted 14 August 2026 by the employer.
About the role
This role focuses on Signal and Power Integrity (SI/PI) for chip package and PCB design analysis to achieve high-speed mixed-signal circuit design challenges, including DP2.1 and PCI-Express Gen6.
What you'll do
- Craft Signal and Power Integrity solutions to complex system design problems.
- Perform system-level power integrity simulations of NVlinks 200Gbs+, PCIe, and other HSIO such as DP2.1/HDMI2.1/CSI/USB4.
- Design and optimize Power Delivery Network (PDN) across interposers, packages, and PCBs.
- Conduct SI channel analysis for spec development, including DP2.1/HDMI FRL2.
- Perform post-layout SI/PI model extraction for project review sign-off.
What you'll need
- BS/MS-Electrical Engineering or equivalent experience with 5+ years of industry experience.
- Strong understanding of electromagnetics, including transmission line theory and via properties, and SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge.
- Hands-on use of 3/2.5-D modeling tools like ANSYS HFSS/Q3D/SIwave, Cadence PowerSI.
- Experience with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations for power noise.
- Experience with die power delivery modeling – mixed-signal blocks & digital and associated tools like CSM/Redhawk, Raptor-X.
- Familiarity with voltage regulator modeling for board power supplies using simplis or spice. Familiarity with use of VNA, TDR, DSO.
Nice to have
- Experience with Matlab, Python, VBS, or C for simulation automation.
- Exposure to interface timing budgets and system modeling.
- SI analysis flow including frequency and time domain simulation.
- PDN analysis flow including model generation and time domain simulation.
- PSIJ Analyses involving co-simulation of circuits and PDN models.
- Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes.
- Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts.
- Understanding of high-volume manufacturing variations and impact to channel signal integrity.
Skills: Signal and Power Integrity, system-level power integrity simulations, PCI-Express Gen6, HSIO, PDN
This role has been open 46 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 31 | 1385 · 107 employers |
| Median days open | 115 d | 76 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Signal and Power Integrity, system-level power integrity simulations, PCI-Express Gen6, HSIO, PDN
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA (this employer) · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.