Senior Serdes System Design Engineer/Architect - United States
$121,900 - $195,000 USD yearly
Originally posted 2 September 2026 by the employer.
About the role
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+.
What you'll do
- Develop channel models and run simulations to define Serdes architecture.
- Define and document signal processing block requirements, architecture, and lab test plan.
- Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
- Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs.
- Work with the design team to perform vector matching verification with RTL simulations.
- Develop, test, and debug firmware associated with physical layer functionality.
- Perform lab testing and debug of Serdes.
What you'll need
- B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years relevant experience.
- Expert knowledge in Communication Theory.
- Expert knowledge in Digital Signal Processing algorithms.
- Working knowledge of Analog circuit behavior.
- Working knowledge of Transmission line theory and s-parameter.
- Expert in MATLAB, C/C++ programming.
- Good hands-on skills in the lab.
Nice to have
- Experience in designing high-speed Clock and Data Recovery (CDR) PLLs.
- Experience in equalization techniques for wireline communication applications such as read-channel.
- RTL coding experience.
- Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards.
- Knowledge of PCIe Gen6/Gen7 standards.
Skills: high-speed Serdes, DSP algorithms, PAM modulation, adaptive equalizers, MATLAB/C++ system models, channel models
This role has been open 27 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
238
|
Median days open
78 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (238 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 238 |
| Open roles in the wider Analog & Mixed-Signal family | 42 | 1385 · 107 employers |
| Median days open | 161 d | 78 d (+83 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: high-speed Serdes, DSP algorithms, PAM modulation, adaptive equalizers, MATLAB/C++ system models, channel models
Who's hiring in this category
- AMD · 27 open roles · median 66 d
- Synopsys · 25 open roles · median 46 d
- Qualcomm · 20 open roles · median 57 d
- Cadence Design Systems · 18 open roles · median 180 d
- Micron Technology · 11 open roles · median 75 d
- Apple · 10 open roles · median 12 d
How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.