Senior Scale-Up Network System Architect - CA, Santa Clara, United States
$184,000 - $356,500 USD yearly
Originally posted 4 October 2026 by the employer.
Architect NVLink-based scale-up networking.
About the role
As a Senior Scale-Up Network System Architect, you will develop the complete architecture of interconnects that link GPUs within and between racks for AI supercomputing platforms. This role focuses on fabric enabling sizable AI training and inference clusters to function as a single large accelerator.
What you'll do
- Convert AI training and inference workload needs (LLM, MoE, and emerging model architectures) into specific networking, bandwidth, latency, and resiliency specifications.
- Drive architecture trade-off studies across performance, cost, power, and reliability, and build models to justify decisions with data.
- Collaborate with ASIC, firmware, software, and systems teams to ensure architecture decisions are implementable in silicon and product.
- Develop and use simulation and analytical models to validate architecture choices before committing to silicon.
- Represent system architecture in technical discussions and serve as a technical expert on scale-up network behavior at scale.
What you'll need
- Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
- 8+ years of industry experience in computer networking, system architecture, or high-performance interconnects.
- Strong grasp of network structure and dynamics at scale, including the impact of topology, congestion, and failure modes on distributed workload performance.
- Experience developing or using simulation/modeling environments to evaluate architecture trade-offs.
- Strong multi-functional collaboration skills.
- Clear technical communication, including the ability to explain complex architecture trade-offs.
Skills: interconnect architecture, NVLink scale-up networks, AI training and inference clusters, topology, simulation and analytical models
This role has been open 4 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 60 | 461 |
| Open roles in the wider Digital Design & Verification family | 231 | 3183 · 114 employers |
| Median days open | 63 d | 76 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: interconnect architecture, NVLink scale-up networks, AI training and inference clusters, topology, simulation and analytical models
Who's hiring in this category
- Qualcomm · 77 open roles · median 79 d
- NVIDIA (this employer) · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.