Senior RTL Silicon Design & Validation Engineer - Hyderabad-Sattva, India
Originally posted 2 March 2026 by the employer — open 192 days. Relisted by the employer on 6 July 2026.
This role focuses on designing and validating PCIe Gen6/Gen7 and CXL technologies.
About the role
This role involves designing, planning, and executing RTL design for new and existing PCIe technology and solutions for programmable silicon.
What you'll do
- Develop and productize PCIe, CXL, and connectivity solutions.
- Participate in all phases of product development from architecture through implementation, prototyping, validation, productization, and support.
- Develop comprehensive testing plans, including Compliance and Interop testing.
- Perform Pre-Silicon and Post Silicon validation for new PCIe enabled blocks.
- Be responsible for IP design, Silicon bring up, Validation, and IP release.
What you'll need
- Bachelor's or Master's degree in Computer Engineering/Electrical Engineering with 8+ years of experience.
- Knowledge of high-speed interfaces including PCIe, CXL, NVMe, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocol.
Nice to have
- Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog.
- Proficient in RTL simulation tools (VCS, Modelsim).
- Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer.
- Experience in developing system or IP prototypes using FPGAs.
- Strong knowledge of IP/SOC design methodologies.
- Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles.
- Knowledge of C/C++.
Skills: PCIe Gen6/Gen7, CXL, RTL design, Verilog, SystemVerilog, high-speed interfaces
This role has been open 171 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 24 | 217 |
| Median days open | 61 d | 91 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PCIe Gen6/Gen7, CXL, RTL design, Verilog, SystemVerilog, high-speed interfaces
Who's hiring in this category
- AMD (this employer) · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.