Senior RTL Engineer - Santa Clara, CA, United States

Originally posted 15 July 2026 by the employer.

About the role

What you'll do

• Own the design, implementation, and optimization of RTL for key portions of the SoC.
• Collaborate with architects to develop robust microarchitectures and drive microarchitectural decisions.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, and runtime software.
• Work with software teams to define hardware interfaces, execution flows, and memory hierarchies.
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic.
• Optimize designs for performance, power, area, scalability, and reliability.

What you'll need

• 8+ years designing RTL for complex digital systems with ownership of significant blocks or subsystems through tapeout.
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
• Expert-level Verilog/SystemVerilog and modern RTL design methodologies (lint, CDC, synthesis-aware coding, low-power intent).
• Strong grasp of performance, power, and area tradeoffs, and experience making data-driven microarchitecture decisions.
• Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
• Experience with hardware/software co-design and system-level performance optimization.
• Strong debugging and problem-solving skills.

Nice to have

• Deep expertise in memory subsystem design: caches, coherency, memory controllers (LPDDR/DDR/HBM), on-chip SRAM organization, address translation, and memory protection.
• Hands-on experience designing or significantly extending DMA engines, data-movement accelerators, or similar high-bandwidth data-path logic, including descriptor-based DMA, multi-channel arbitration, QoS, and outstanding-transaction management.
• Working knowledge of standard interconnect and coherency protocols (AXI, CHI, ACE) and their performance implications.
• Experience with SMMU/IOMMU design or integration, virtualization, and DMA isolation for safety or security.
• Familiarity with RAS features in memory and data paths, such as ECC, poisoning, and error reporting.
• Experience with NoC fabrics, virtual channels, and QoS mechanisms for memory traffic.
• Knowledge of functional safety (ISO 26262/ASIL) as it applies to memory and data-path design.
• Experience with AI, machine learning, or edge AI hardware, especially tensor data-movement patterns and tiling strategies.
• Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
• Knowledge of low-power design techniques and power management architectures.
• Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
• Background in CPUs and memory subsystems, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and advanced driver-assistance systems (ADAS), aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.