Senior RTL Engineer, Memory Centric Computing - San Jose, California, United States
Originally posted 19 August 2026 by the employer.
Design IP for Memory Centric Computing systems.
About the role
This role involves developing and optimizing IP for memory centric computing systems. The AGI Computing Lab focuses on solving system-level challenges for AI/ML workloads.
What you'll do
- Develop IP for memory centric computing systems using Verilog, System Verilog and HLS.
- Optimize IP for performance, power, and area using advanced design techniques.
- Collaborate with Verification engineers to design and develop test plans.
- Make design decisions across performance, power, thermal, and cost.
- Troubleshoot and debug hardware issues through verification and validation.
- Contribute to the development of new technologies in machine learning and hardware architecture.
What you'll need
- 5+ years of industry experience (Bachelor's with 5+, Master's with 3+, or PhD with 0+ years).
- Strong background in microarchitecture and computer architecture.
- 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs.
- Experience in designing Memory Controller, NOC, Interconnect IP.
- Experience in Memory Centric computing IP and SOC integration.
- Experience in AI/ML workloads.
This role has been open 46 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 968 |
| Open roles in the wider Digital Design & Verification family | 13 | 3109 · 114 employers |
| Median days open | 46 d | 62 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.