Senior RTL Engineer, IO Die and Interconnect IP - San Jose, California, United States

Originally posted 21 August 2026 by the employer.

This role involves developing RTL for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP.

About the role

This role involves designing and developing scalable platforms that can effectively handle the computational and memory requirements of AI/ML workloads while minimizing energy consumption and maximizing performance. The team focuses on emerging technologies and trends across memory, computing, interconnect, and AI/ML.

What you'll do

• Develop RTL (Verilog/SystemVerilog) for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP into a cohesive chiplet-based architecture.
• Integrate internal and third-party interconnect IP — UCIe, PCIe, CXL, die-to-die, and NoC — into the IO die.
• Modify and customize PCIe and other interconnect IP as needed to meet die-level requirements and close functional gaps.
• Define and implement die-to-die and chiplet interfaces using UCIe, ensuring protocol compliance and interoperability.
• Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges.
• Collaborate with verification, architecture, PHY/SerDes, physical design, and software teams to close requirements across performance, power, area, and interoperability.
• Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks.

What you'll need

• Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.
• Strong background in microarchitecture and RTL design for complex SoC and die integration.
• 5+ years of experience in RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems.
• Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces.
• Experience modifying or customizing third-party interconnect IP (e.g., PCIe controller, PIPE, or PHY interface) to meet die-level requirements.
• Familiarity with UCIe and chiplet-based, multi-die architectures and die-to-die interconnect.
• Solid understanding of PCIe/CXL protocol stacks (transaction, data link, and physical layers) and the PIPE interface.
• Experience with SoC integration methodologies, IP packaging (e.g., IP-XACT), and on-chip interface protocols such as AXI, ACE, CHI, or APB.
• Proficiency in scripting (Tcl, Python, or Perl) for design integration and automation.
• Experience in AI/ML workloads.

Nice to have

• Familiarity with agentic AI tools and frameworks.