Senior RTL Design Engineer with Memory controllers
This role focuses on the design and validation of AMD’s DDR IPs.
Originally posted 15 September 2026 by the employer.
About the role
This role focuses on planning, building, and executing the design and validation of new and existing features for AMD’s DDR IPs and custom IPs. This involves collaborating with cross-functional teams to design and integrate DDR memory controller calibration solutions, including RTL logic, firmware routines, and algorithmic flows.
What you'll do
- Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards.
- Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions.
- Create and execute validation plans to verify the correctness and performance of calibration firmware, algorithms, and custom IPs.
- Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability.
- Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements.
- Stay updated with emerging DDR technologies and calibration techniques, proposing and implementing innovative solutions.
What you'll need
- 5+ years of relevant experience in digital design and RTL design in Verilog/SystemVerilog.
- Knowledge of system-level architecture, including buses like AXI/AHB and bridges.
- Experience with circuit timing/STA and practical experience with tools.
- Working knowledge of C.
- Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards.
- Experience with implementing DRAM/memory controller initialization code and memory subsystem/DDR PHYs training/calibration software.
- Experience with version control systems such as Perforce, ICManage, or Git.
Nice to have
- Embedded experience.
- Familiarity with industry standard lab tools such as high speed scope, compliance packages, or logic analyzers.
More semiconductor jobs: AMD jobs · RTL design jobs · India jobs
This role has been open 50 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1086
|
Median days open
61 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1086 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 79 | 1086 |
| Open roles in the wider Digital Design & Verification family | 248 | 3497 · 120 employers |
| Median days open | 47 d | 61 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 71 d
- Synopsys · 90 open roles · median 48 d
- AMD (this employer) · 78 open roles · median 47 d
- NXP Semiconductors · 45 open roles · median 104 d
- NVIDIA · 44 open roles · median 61 d
- Analog Devices · 41 open roles · median 51 d
How we counted: 1086 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.