Senior RTL Design Engineer

Originally posted 14 October 2026 by the employer.

Design, integrate, and sign off RTL for blocks across power-efficient SoCs, including compute fabric on-chip interconnect and memory interfaces.

About the role

As a Senior RTL Design Engineer, you will design, integrate, and sign off RTL for blocks across Efficient Computer's power-efficient SoC: the compute fabric's on-chip interconnect and memory interfaces, low-power and always-on logic, and standard peripheral IP (RISC-V, NVM, I2S, I2C).

What you'll do

• Implement microarchitecture and RTL for assigned blocks in the compute fabric, on-chip networks/NoC, memory interfaces, and peripheral subsystems.
• Integrate third-party and in-house IP (RISC-V cores, NVM controllers, SRAM wrappers, I2S/I2C/APB peripherals) at the subsystem and SoC level.
• Own block-level front-end quality: lint-clean RTL, CDC and RDC analysis, and LEC between RTL and netlist.
• Run synthesis, write and maintain SDC timing constraints, and analyze STA reports to meet timing, area, and power targets.
• Implement low-power RTL per UPF intent: power domains, isolation, level shifters, retention, and fine-grained clock gating.
• Run block-level simulations and debug failures alongside the DV team; contribute directed test scenarios.

What you'll need

• 8-10 years of front-end digital design experience on processor, accelerator, or SoC products.
• Significant contributions to at least two tapeout cycles.
• Strong proficiency in SystemVerilog for synthesizable RTL.
• Hands-on experience with standard VLSI front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, isolation, and retention.
• Working knowledge of at least one on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL level.
• Experience with on-chip memories: SRAM wrappers, banking, and memory-mapped register interfaces.
• Comfortable running RTL simulations and debugging with waveform tools.

Nice to have

• Experience designing or integrating on-chip networks, dataflow pipelines, or memory subsystems.
• Familiarity with NVM controller RTL (MRAM, RRAM, etc.), including ECC and program/erase sequencing.
• Experience with very low power design techniques and the RTL design choices they require.
• Understanding of parallel execution models such as dataflow, SIMD, or systolic arrays.
• Experience with RTL and gate-level power analysis tools and methodologies.
• Exposure to DFT concepts: scan insertion, ATPG, and DFT-friendly RTL coding.
• Scripting skills (Python, Tcl, Perl) to automate design flows.