Originally posted 6 August 2026 by the employer.
About the role
As an RTL Design Engineer at Mueon, you will develop digital logic for AI computing platforms. Working closely with architecture, verification, physical design, and DFT teams, you will implement synthesizable RTL meeting performance, power, and area requirements.
What you'll do
- Design and develop synthesizable RTL using Verilog and SystemVerilog for digital IP blocks and SoC subsystems.
- Translate architectural and microarchitecture specifications into efficient, low-power hardware implementations.
- Collaborate with verification engineers to develop verification plans, review functional coverage, and resolve design issues.
- Drive RTL quality through lint, clock domain crossing (CDC), and reset domain crossing (RDC) analysis and resolution.
- Partner with synthesis and physical design teams to optimize designs for timing, power, area, and manufacturability.
- Support post-silicon bring-up, debug, and root-cause analysis as products transition into hardware.
What you'll need
- B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- 3-5 years of experience developing RTL for ASIC or FPGA designs.
- Proficiency with Verilog and/or SystemVerilog for RTL development.
- Solid understanding of digital logic design, synchronous design techniques, and computer architecture.
- Experience with simulation tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, or equivalent.
- Familiarity with lint, CDC, and RDC verification methodologies.
- Working knowledge of synthesis, static timing analysis, DFT, and physical implementation flows.
- Experience with scripting languages such as Python, Tcl, or Perl.
Nice to have
- Experience with industry-standard bus protocols including AXI, AHB, APB, PCIe, CXL, or UCIe.
- Experience developing low-power RTL using clock gating, power gating, multi-voltage design techniques, or UPF.
- Familiarity with formal verification, equivalence checking, or assertion-based verification methodologies.
- Experience designing high-speed interfaces including DDR, HBM, Ethernet, SerDes, or other high-performance interconnects.
- Experience with Git, IP-XACT, or reusable IP development methodologies.
- Experience developing AI accelerators, CPUs, GPUs, or networking ASICs.
More semiconductor jobs: RTL design jobs · Hillsboro jobs
First seen in our index 0 days ago, well below the 65-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1098
|
Median days since first seen
65 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Mueon | All employers we track in this specialty (1098 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1098 |
| Open roles in the wider Digital Design & Verification family | 8 | 3506 · 120 employers |
| Median days since first seen | 0 d | 65 d (+65 d vs this employer) |
| Median salary (USD postings) | n/a | $188k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 74 d
- AMD · 92 open roles · median 55 d
- Synopsys · 89 open roles · median 54 d
- NVIDIA · 48 open roles · median 67 d
- NXP Semiconductors · 45 open roles · median 110 d
- Analog Devices · 40 open roles · median 57 d
How we counted: 1098 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.