Senior RTL Design Engineer - Austin, Texas, United States
$120,000 USD yearly
Originally posted 20 August 2026 by the employer.
Design component units of the Reconfigurable Dataflow Unit (RDU) ASICs.
About the role
SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. This role contributes to the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator.
What you'll do
- Own blocks within a larger subsystem, contributing sections of the microarchitecture specification
- Write and debug RTL
- Carry blocks through implementation, tape-out, and silicon bring-up
- Work alongside principal engineers, architects, design verification, and physical design
What you'll need
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 5+ years of experience in ASIC RTL design
- Solid foundation in computer architecture and digital logic design
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
- Experience making design decisions that trade off power, performance, and area
- Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- Experience with digital logic synthesis tools and static timing analysis
- Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
- Experience implementing SystemVerilog Assertions to check design intent
- Familiarity with tools and simulators for hardware performance analysis and tuning
- Familiarity with Git for managing release cycles
- Scripting skills in Python and Linux shell
Nice to have
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Exposure to a full ASIC development cycle through tape-out and production silicon
- Interest in or knowledge of AI workload acceleration techniques
- Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation
This role has been open 57 days — below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1021 |
| Open roles in the wider Digital Design & Verification family | 7 | 3198 · 115 employers |
| Median days open | 58 d | 62 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 62 d
- Synopsys · 85 open roles · median 30 d
- AMD · 71 open roles · median 36 d
- Analog Devices · 48 open roles · median 50 d
- NVIDIA · 46 open roles · median 64 d
- NXP Semiconductors · 41 open roles · median 85 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.