Senior R&D Device Test and Characterization Engineer - Scottsdale, AZ, United States
Verification, Validation & Test
Originally posted 25 August 2026 by the employer.
About the role
This role involves supporting semiconductor technology development through wafer-level electrical characterization, reliability testing, and test automation in the Scottsdale Device Characterization Laboratory.
What you'll do
- Perform wafer-level electrical characterization and reliability testing using SMUs (such as B1500) and Semi and Fully-automatic probe stations, including I-V, C-V, breakdown-voltage, leakage-current, HTRB, HCI, TDDB, RTS, and low-frequency-noise measurements.
- Develop new device characterization test routines and procedures for emerging technologies.
- Translate engineering requests into accurate test configurations, execute measurements, validate data quality, identify abnormal results, and deliver timely, traceable reports.
- Develop and maintain Python scripts for instrument control, wafer stepping, automated test execution, data processing, visualization, and analysis of large semiconductor data sets.
- Integrate AI, machine learning, statistical analysis, and anomaly-detection methods into testing workflows to improve data review, test efficiency, equipment utilization, and report generation.
- Own assigned test systems and support equipment scheduling, calibration, preventive maintenance, upgrades, troubleshooting, wafer traceability, laboratory compliance, and user training.
What you'll need
- Bachelor's degree or higher in Electrical Engineering, Semiconductor Engineering, Physics, Materials Science, Computer Engineering, or a closely related field, or equivalent relevant industry experience.
- Hands-on experience with semiconductor wafer-level characterization, semi-automatic probe stations, and semiconductor parameter analyzers such as the Keysight B1500A or B1505A, Keithley K2612, 2657, or similar.
- Practical knowledge of semiconductor devices, electrical characterization, reliability testing, high-voltage measurements, low-current measurements, and temperature-dependent testing.
- Proficiency in Python, including independent development and debugging of scripts for instrument control, test automation, data processing, visualization, and analysis of large data sets.
- Familiarity with Python engineering libraries such as NumPy, pandas, SciPy, and Matplotlib, and with instrument-control protocols or test-automation platforms.
- Ability to troubleshoot integrated hardware and software systems and distinguish valid device behavior from measurement noise, setup errors, equipment limitations, or data-processing issues.
- Working knowledge of statistics and an interest in applying AI and machine learning to anomaly detection, pattern recognition, predictive maintenance, test optimization, and engineering reporting.
Market context
This role has been open 33 days — slightly above the 25-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
472
|
Median days open
25 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (472 roles · 72 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 472 |
| Open roles in the wider Silicon Validation & Test family | 75 | 2149 · 110 employers |
| Median days open | 26 d | 25 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 50 open roles · median 10 d
- Infineon Technologies · 37 open roles · median 32 d
- Renesas Electronics · 33 open roles · median 28 d
- AMD · 26 open roles · median 26 d
- Micron Technology · 25 open roles · median 28 d
- Qualcomm · 25 open roles · median 13 d
How we counted: 472 open Silicon Test Engineering (DFT Test) roles from 72 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.