Senior Product, Test and Yield Enhancement Engineer - Taiwan - Sunnyvale, CA, United States
Originally posted 30 September 2026 by the employer.
Drive the test strategy for future generations of the Cerebras Wafer Scale Engine.
About the role
This role drives the test strategy for future generations of the Cerebras Wafer Scale Engine in Taiwan, spanning AI processors, high-speed I/O and memory.
What you'll do
- Develop and optimize production test programs for wafer-scale AI processors.
- Drive high-volume manufacturing testing in partnership with foundries and outsourced semiconductor assembly and test providers (OSATs).
- Implement and optimize design-for-test strategies, including scan, built-in self-test (BIST), automatic test-pattern generation (ATPG) and functional testing.
- Analyze automated test equipment (ATE), Shmoo, parametric and defect data to improve yield and fault tolerance.
- Develop failure-analysis and fault-isolation methods for defective cores, tiles and other functional blocks.
- Build efficient wafer-level test flows for massively parallel compute, mesh and network-on-chip architectures, and die-to-die interconnects.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering or a related field.
- 10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
- Strong experience in test development, silicon debug, test optimization and yield improvement.
- Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM.
- Expert-level, hands-on experience with the Advantest V93000 platform.
- Experience specifying, designing, developing and debugging load boards and probe cards for advanced production-test and DFT requirements.
Nice to have
- Programming experience with C, C++, Python or Perl for large-scale test-data analysis.
- Experience with semiconductor test and failure-analysis tools or techniques such as Tessent, OBIRCH, IREM and LADA.
- Experience testing high-speed SerDes at the ATE, package or system level.
- Experience with analog blocks embedded within large digital ASICs.
- Experience applying advanced data-analysis or machine-learning techniques to yield optimization.
- Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics and defect-mitigation techniques.
- Teradyne experience is a plus.
This role has been open 9 days — well below the 24-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
523
|
Median days open
24 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Cerebras | All employers we track in this specialty (523 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 523 |
| Open roles in the wider Silicon Validation & Test family | 3 | 2209 · 111 employers |
| Median days open | 9 d | 24 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Who's hiring in this category
- Teradyne · 67 open roles · median 21 d
- Infineon Technologies · 39 open roles · median 35 d
- Renesas Electronics · 39 open roles · median 24 d
- AMD · 28 open roles · median 36 d
- Micron Technology · 28 open roles · median 30 d
- Qualcomm · 25 open roles · median 23 d
How we counted: 523 open Silicon Test Engineering (DFT Test) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.