Senior Product Engineer , PrimeTime Signoff Solutions
Originally posted 11 October 2026 by the employer.
Drive production deployment of PrimeTime capabilities including HyperGrid distributed STA, native IR-aware timing analysis, thermal-aware signoff, aging analysis, and multi-die timing closure at strategic semiconductor customers.
About the role
This role involves driving the production deployment of PrimeTime capabilities and leading technical engagements with design teams at strategic accounts. You will partner with R&D teams to evaluate new architectures and own beta programs from kickoff through production readiness.
What you'll do
- Drive production deployment of PrimeTime capabilities including HyperGrid distributed STA, native IR-aware timing analysis, thermal-aware signoff, aging analysis, and multi-die timing closure at strategic semiconductor customers
- Lead direct technical engagements with design teams at accounts, translating advanced-node challenges into product requirements and deployment strategies
- Partner with R&D teams to evaluate new architectures like cloud-native PrimeTime and AI-assisted constraint generation, validating functionality and identifying performance bottlenecks
- Own beta programs and pre-production evaluations from kickoff through production readiness, defining test plans and tracking results
- Resolve critical customer escalations through structured root-cause analysis, building effective workarounds and driving long-term fixes back into the product
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline
- Deep hands-on experience with PrimeTime or comparable timing signoff tools across multiple production tapeouts, including multi-corner multi-mode analysis, variation modeling, and advanced-node signoff challenges
- Strong understanding of static timing analysis fundamentals including setup/hold analysis, clock domain crossing, false paths, multi-cycle paths, and constraint methodology
- Proficiency in Tcl and Python for automation, analysis, and debugging of complex timing scenarios
- Track record of solving technical problems in EDA, ASIC/SoC design, or physical implementation environments
- Experience with distributed computing, cloud infrastructure, or HyperGrid technologies
Skills: PrimeTime, timing signoff, static timing analysis, HyperGrid, Tcl, Python
This role has been open 2 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 64 | 688 |
| Open roles in the wider Physical Implementation family | 107 | 1470 · 108 employers |
| Median days open | 40 d | 78 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: PrimeTime, timing signoff, static timing analysis, HyperGrid, Tcl, Python
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 168 d
- Synopsys (this employer) · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.