Senior Principal Software Engineer - San Jose, United States
$161,000 - $299,000 USD yearly
Originally posted 25 September 2026 by the employer.
About the role
This role involves enhancing and supporting the Xcelium RTL/logic simulator engine.
What you'll do
- Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
- Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.
- Design, tune, and innovate graph algorithms involving SDC constraints support on multi‑billion‑node graphs.
- Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
- Collaborate with global team members to deliver high-quality results.
- Write Specifications and Unit Tests for your code.
What you'll need
- MS/PhD in Computer Science or Electrical Engineering.
- Minimum of 7 years of experience with an MS or 5 years of experience with a PhD.
- 5+ years of experience in EDA software development.
- Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis, especially path exceptions handling in a STA tool.
- Excellent programming skills in C/C++.
- Deep understanding of SystemVerilog or Verilog.
- Experience in multi-threaded/concurrent programming.
- Ability to quickly learn new technologies and adapt to project requirements.
Nice to have
- Prior experience with RTL/logic simulation software development.
Skills: Xcelium simulator, RTL/logic simulation, C++, SystemVerilog, Timing Constraints Verification
This role has been open 15 days — well below the 79-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
692
|
Median days open
79 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (692 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 160 | 692 |
| Open roles in the wider Physical Implementation family | 183 | 1473 · 107 employers |
| Median days open | 168 d | 79 d (+89 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: Xcelium simulator, RTL/logic simulation, C++, SystemVerilog, Timing Constraints Verification
Who's hiring in this category
- Cadence Design Systems (this employer) · 161 open roles · median 165 d
- Synopsys · 59 open roles · median 37 d
- Micron Technology · 42 open roles · median 90 d
- Qualcomm · 42 open roles · median 61 d
- NVIDIA · 41 open roles · median 74 d
- GlobalFoundries · 31 open roles · median 51 d
How we counted: 692 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.