Senior/Principal Interface IP Verification Engineer (Pre-Silicon) - 18386
Originally posted 13 August 2026 by the employer. Relisted by the employer on 26 September 2026.
Verify PCIe, CXL, DDR, and Ethernet technologies for Interface IP solutions.
About the role
This role involves verifying complex Interface IP solutions and solving challenging protocol issues.
What you'll do
- Own verification of complex Interface IP solutions, including PCIe, CXL, DDR, and Ethernet technologies.
- Architect, develop, and enhance scalable UVM-based verification environments and reusable verification IP.
- Define verification strategies and test plans from specification review through product release.
- Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM.
- Drive functional coverage closure and verification signoff activities.
- Debug challenging RTL, protocol, and system-level issues.
What you'll need
- BSEE with at least 8 to 10+ years of direct industry experience verifying complex ASIC or SoC designs.
- Deep expertise with SystemVerilog and UVM methodologies.
- Strong protocol knowledge in one or more of the following areas: PCI Express (PCIe), Compute Express Link (CXL), DDR Memory Interfaces, Ethernet.
- Experience developing constrained-random and coverage-driven verification environments.
- Strong debugging and problem-solving skills spanning RTL, verification, and protocol compliance.
- Experience with industry-standard simulators such as VCS, ModelSim, or similar tools.
Nice to have
- Experience with verification IP development, assertion-based verification and formal methodologies.
- Knowledge of modern SoC architectures and high-speed communication interfaces.
Skills: UVM, SystemVerilog, PCIe, CXL, DDR
This role has been open 62 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 64 | 1205 |
| Open roles in the wider Digital Design & Verification family | 171 | 3198 · 115 employers |
| Median days open | 32 d | 64 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, PCIe, CXL, DDR
Who's hiring in this category
- Qualcomm · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys (this employer) · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.