Senior Principal Hardware Emulation Engineer - San Jose, California, United States
$210,000 - $280,000 USD yearly
Originally posted 18 August 2026 by the employer.
SambaNova is looking for a Senior Principal Engineer to build and own hardware emulation models for the RDU.
About the role
SambaNova is looking for a Senior Principal Engineer to build and own the hardware emulation models for the Reconfigurable Dataflow Unit (RDU), the silicon behind AI workload acceleration systems.
What you'll do
- Develop emulation models for new RDU generations, including high-performance transactors, behavioral models, and memory models in SystemVerilog and C/C++.
- Partner with the RTL design team to ensure designs are emulation-compliant by reviewing RTL and IP for constructs that do not map cleanly to the emulator.
- Own model fidelity, ensuring substituted and custom models closely track design intent for software, performance, and verification results.
- Build and own the workflows that automate emulation testing, including job scheduling, regression launch, failure triage, and results reporting.
- Own throughput and capacity, profiling and removing bottlenecks in models, transactors, and testbench collateral.
- Manage the emulator vendor relationship, driving blocking tool issues to resolution and advising on platform selection.
What you'll need
- B.S. in Electrical Engineering, Computer Engineering, or Related Field.
- 10+ years of professional experience, including hands-on emulation work.
- Hands-on expertise bringing up and sustaining designs on an industry-standard emulation platform such as Palladium, Veloce, or Zebu, including compile flows, partitioning, debug capabilities, and performance tuning.
- Strong SystemVerilog and C/C++ for building transactors, behavioral models, memory models, and co-emulation infrastructure.
- Experience making a design emulation-ready by identifying RTL and IP issues and resolving them with vendor emulation models or custom code.
- Track record owning an emulation platform across at least one full chip program, from bring-up through tape-out, enabling software teams to run a real stack against the pre-silicon model.
- Track record owning an emulator vendor relationship, driving blocking tool issues and evaluating new platform capabilities.
- Experience applying emulation to performance analysis, accelerating functional verification regressions, or both.
- Debug ability across the hardware/software boundary to localize failures.
- Scripting and automation in Python and shell for building regression, scheduling, and triage workflows.
- Demonstrated technical leadership without formal authority, setting methodology direction across design, verification, and software teams.
Nice to have
- M.S. or PHD in Electrical Engineering, Computer Engineering, or Related Field.
- Depth on Cadence Palladium.
- Hands-on experience on more than one emulation platform.
- Machine learning accelerators, dataflow architectures, or reconfigurable dataflow units.
Skills: hardware emulation, SystemVerilog, Palladium, Veloce, Zebu, RTL design
This role has been open 59 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1205 |
| Open roles in the wider Digital Design & Verification family | 7 | 3198 · 115 employers |
| Median days open | 59 d | 64 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: hardware emulation, SystemVerilog, Palladium, Veloce, Zebu, RTL design
Who's hiring in this category
- Qualcomm · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.