Senior | Principal Foundry Interface Design Engineer - HBM- TPG
$181,000 - $308,000 USD yearly
Originally posted 12 November 2026 by the employer.
About the role
Provide critical technology support for the design and development of HBM DRAM products within the HBM Design Architecture team. You will serve as a bridge between internal design teams, foundries, and technology development groups to translate advanced process capabilities into high-performance memory architectures.
What you'll do
- Drive foundry interface and technology alignment, evaluating foundry collateral and aligning process capabilities with design requirements.
- Execute circuit simulation and analysis using HSPICE, standard cell benchmarking, and PPA analysis.
- Support test-chip and silicon validation along with parasitic extraction and physical verification.
- Manage PDK and design enablement to ensure design flows and collateral integrate smoothly with internal build teams.
- Implement AI-enabled engineering practices and automation to improve DTCO analysis efficiency, PDK enablement, and benchmarking.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of semiconductor industry experience with an understanding of advanced semiconductor technology development.
- Demonstrated experience in advanced CMOS technology nodes, FinFET devices, and process integration.
- Hands-on experience with HSPICE simulations, device characterization, standard cell benchmarking, PPA analysis, parasitic extraction, and physical verification.
- Experience driving automation and AI-enabled engineering practices to support DTCO analysis, foundry collateral evaluation, and PDK enablement.
Nice to have
- Experience working directly with foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
- Experience with memory products including DRAM, HBM, or SRAM.
- Knowledge of TSV technologies, advanced packaging, reliability modeling, aging simulations, advanced BEOL technologies, and PDK development and validation.
- Ability to apply AI tools to summarize, analyze, and extract insights from PDK documentation, Design Rule Manuals (DRMs), reliability reports, foundry collateral, and silicon characterization data.
- Experience leading technology pathfinding and node selection activities.
More semiconductor jobs: Micron Technology jobs · EDA tools engineer jobs · California jobs
First seen in our index 0 days ago, well below the 69-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
745
|
Median days since first seen
69 d
|
Category median salary (all employers)
$186k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (745 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 51 | 745 |
| Open roles in the wider Physical Implementation family | 78 | 1646 · 118 employers |
| Median days since first seen | 36 d | 69 d (+33 d vs this employer) |
| Median salary (USD postings) | n/a | $186k |
Who's hiring in this category
- Cadence Design Systems · 160 open roles · median 162 d
- Synopsys · 61 open roles · median 55 d
- Micron Technology (this employer) · 48 open roles · median 45 d
- NVIDIA · 45 open roles · median 107 d
- Renesas Electronics · 41 open roles · median 20 d
- Qualcomm · 36 open roles · median 91 d
How we counted: 745 open EDA/CAD Engineering (EDA Tools) roles from 78 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.