Senior Principal Engineer, Signal Integrity & Power Integrity (SerDes IP)
Originally posted 20 October 2026 by the employer.
Focus on SI/PI strategies and channel design for PCIe and Ethernet SerDes IP.
About the role
This role leads Signal Integrity and Power Integrity investigations and technical execution for SerDes IP across silicon, package, board, and system environments. The position is part of the Silicon IP team developing SerDes solutions for AI, cloud, networking, HPC, and optical communications systems.
What you'll do
- Lead Signal Integrity and Power Integrity investigations and drive resolution of complex design challenges. - Define and execute SI/PI strategies for SerDes products, including package, channel, and 3DIC considerations. - Develop and maintain SI/PI requirements for PCIe and Ethernet products across chip, package, board, and system levels. - Perform channel feasibility analysis, modeling, simulation, and correlation activities. - Review and sign off SI/PI aspects of SerDes transmitter, receiver, and test chip designs. - Collaborate with architecture, design, package, and applications engineering teams, and support customer technical debug activities.
What you'll need
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering with at least 15+ years of direct industry experience. - Proven experience in Signal Integrity and Power Integrity for high-speed SerDes designs. - Expertise in PCIe and/or Ethernet systems and channel design. - Strong knowledge of NRZ/PAM4 signaling, S-parameter modeling, and SI simulation methodologies. - Experience with HFSS, ADS, HSpice, MATLAB, and IBIS-AMI. - Understanding of package, substrate, and PCB technologies.
Skills: Signal Integrity, Power Integrity, SerDes, PCIe, HFSS, PAM4
This role has been open 0 days — well below the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
234
|
Median days open
72 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (234 roles · 46 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 234 |
| Open roles in the wider Analog & Mixed-Signal family | 48 | 1428 · 107 employers |
| Median days open | 36 d | 72 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Signal Integrity, Power Integrity, SerDes, PCIe, HFSS, PAM4
Who's hiring in this category
- Synopsys (this employer) · 31 open roles · median 36 d
- AMD · 26 open roles · median 40 d
- Qualcomm · 20 open roles · median 63 d
- Cadence Design Systems · 19 open roles · median 155 d
- Micron Technology · 15 open roles · median 36 d
- Apple · 12 open roles · median 22 d
How we counted: 234 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 46 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.