Senior Principal Engineer, Physical Designer
$177,820 - $266,400 USD yearly
Originally posted 29 October 2026 by the employer.
About the role
As a senior leader in the central physical design team, you will drive physical design and methodology for high-performance processor chips targeted at server and networking applications.
What you'll do
- Shape the long-term vision for physical design capabilities and infrastructure in alignment with technology strategy.
- Lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS).
- Provide strategic leadership and technical direction to physical design teams to ensure timely tapeouts of complex SoCs.
- Oversee team structure, hiring, performance management, and career development while mentoring engineering talent.
- Drive cross-functional collaboration with design teams to influence design decisions and resolve project conflicts.
- Develop and deploy physical design methodologies, flows, and automation to improve productivity and design quality.
What you'll need
- Bachelor's degree in Computer Science, Electrical Engineering, or related fields with 15+ years of related experience, Master's degree with 10-12 years, PhD with 8-10 years, or equivalent professional experience.
- 15+ years of progressive experience in back-end physical design and verification, including significant leadership roles delivering SoC tapeouts.
- Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges across major foundries.
- Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure.
- In-depth knowledge of modern EDA tools, along with experience developing and deploying physical design methodologies and flows.
- Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl.
Nice to have
- Strong knowledge of static timing analysis (PrimeTime, Tempus), EM/IR-Drop/crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction (Quantus, StarRC), or formal/physical verification (Formality, Verplex, Calibre, Hercules).
- Familiarity with AI/ML-driven optimization in physical design tools.
Skills: Physical Design, RTL-to-GDSII, Place and Route, Timing Closure, Floorplanning
More semiconductor jobs: Marvell Technology jobs · Physical design jobs · Santa Clara jobs
This role has been open 0 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
693
|
Median days open
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (693 roles · 81 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 693 |
| Open roles in the wider Physical Implementation family | 24 | 1545 · 112 employers |
| Median days open | 54 d | 59 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Physical Design, RTL-to-GDSII, Place and Route, Timing Closure, Floorplanning
Who's hiring in this category
- Qualcomm · 114 open roles · median 51 d
- AMD · 63 open roles · median 33 d
- Synopsys · 39 open roles · median 43 d
- Intel Corporation · 38 open roles · median 21 d
- Broadcom · 37 open roles · median 99 d
- NVIDIA · 36 open roles · median 69 d
How we counted: 693 open Physical Design (Physical Design) roles from 81 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.