Senior Principal Engineer – Hardware Chip Lead, Connectivity BU - Santa Clara, CA, United States

Originally posted 30 July 2026 by the employer.

Work on advanced ASICs for hyperscale data centers, enterprise, and AI infrastructure markets, focusing on multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers.

About the role

The ODSP team develops advanced ASICs for hyperscale data center, enterprise, and AI infrastructure markets, including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers, enabling efficient data transmission at 100G+ per lane.

What you'll do

• Serve as the primary hardware technical owner for an ODSP chip program, driving progress from POR through MPR.
• Finalize Product Requirements Documents (PRD) and bring-up requirements in collaboration with architecture, marketing, and applications engineering.
• Coordinate and align cross-functional teams including analog design, digital design, DV, DFT, physical design, STA, firmware, validation, ATE/test engineering, product engineering, and quality.
• Provide technical leadership for the full chip design, defining high-level technical solutions across the hardware stack and resolving complex, cross-disciplinary design challenges.
• Lead end-to-end chip design execution across advanced CMOS nodes (TSMC 2nm/3nm/5nm), including architecture, RTL, physical design, DFT, timing closure, and tape-out.
• Own the chip bring-up plan and execution, coordinating multi-site teams and driving Phase 0, Phase 1, and Phase 2 activities through to silicon validation.

What you'll need

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of related professional experience.
• Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs, from architecture through tape-out and post-silicon productization.
• Deep expertise in high-speed mixed-signal SoC design, including SerDes (100G+/lane), DSP datapath, analog/digital integration, and advanced CMOS process nodes (5nm, 3nm).
• Strong understanding of the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out.
• Experience leading and coordinating cross-functional hardware teams across analog, digital, DV, DFT, PD, firmware, validation, and test engineering disciplines.
• Demonstrated ability to drive silicon bring-up, debug, and validation across multi-site global teams.

Nice to have

• Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimer products.
• Experience with eAVS (Adaptive Voltage Scaling) or similar power optimization subsystems.
• Knowledge of SiPho (Silicon Photonics) integration and module-level validation.
• Experience working in a multi-site, globally distributed engineering organization.

Skills: chip lead, SoC/ASIC programs, high-speed mixed-signal, SerDes 100G+, tape-out, post-silicon productization