Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity
Originally posted 3 June 2026 by the employer. Relisted by the employer on 22 October 2026.
About the role
As Senior Principal Engineer for Signal Integrity and Power Integrity, you will be the senior technical authority responsible for ensuring that customer platforms built on Marvell's Ethernet Switch and UALink silicon meet performance and quality thresholds from prototype through mass production. You will guide SI/PI practices across platforms targeting 112G and 224G PAM4 SerDes designs and systems moving toward 448G.
What you'll do
- Define and maintain layout and routing guidelines for high-speed SerDes channels, power delivery networks, and analog interfaces. - Perform post-silicon channel extraction, full-channel simulation, and what-if analysis on board designs, recommending targeted layout and stack-up adjustments. - Lead compliance testing and lab characterization covering BER/SER, eye-opening margins, jitter, return loss, and crosstalk, translating data into SerDes-tuning guidance. - Run and review power integrity simulations covering PDN impedance, IR drop, decoupling effectiveness, transient response, and droop for high-current ASICs. - Provide hands-on lab debug support during bring-up and ramp using VNAs, BERTs, real-time and sampling oscilloscopes, TDR equipment, and jitter analyzers. - Partner with silicon, packaging, and platform teams while engaging directly with customers and ODMs on design reviews, reference designs, and technical training.
What you'll need
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field. - 15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems. - 10+ years of focused experience in signal integrity and power integrity on high-speed SerDes platforms (25G NRZ through 112G/224G PAM4). - Hands-on expertise across full SI lifecycle tasks: channel modeling, budgeting, layout and stack-up definition, post-layout extraction, and compliance testing. - PI simulation capability across PDN impedance, IR drop, decoupling, transient response, and droop. - Experience with SI/PI EDA toolchains, such as Ansys HFSS/SIwave or Cadence Sigrity/Clarity/PowerSI. - Lab test expertise using VNAs, BERTs, real-time and sampling oscilloscopes, TDR, jitter analyzers, and compliance test kits.
Nice to have
- Direct experience with Ethernet switch platforms or emerging open AI fabric standards and architectures. - Experience supporting SI/PI for platforms targeting megascale data center deployments at production volume. - Background in reference platform SI/PI definition and customer enablement for silicon-based solutions. - Familiarity with ODM/CM design and qualification flows, including DFM/DFT, reliability testing, and high-volume manufacturing variability. - Experience defining SerDes tuning methodologies and correlating simulation, lab, and field-telemetry data. - Familiarity with chip-to-module, copper cable, and connector ecosystems relevant to high-speed Ethernet and AI fabric channels.
Skills: Signal Integrity, Power Integrity, high-speed SerDes platforms, layout guidelines, compliance testing
This role has been open 142 days — well above the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
71 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 29 | 1439 · 106 employers |
| Median days open | 25 d | 71 d (−46 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Signal Integrity, Power Integrity, high-speed SerDes platforms, layout guidelines, compliance testing
Who's hiring in this category
- Synopsys · 36 open roles · median 37 d
- AMD · 27 open roles · median 42 d
- Qualcomm · 21 open roles · median 66 d
- Cadence Design Systems · 20 open roles · median 148 d
- Micron Technology · 15 open roles · median 39 d
- Apple · 9 open roles · median 25 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.