Senior Principal Engineer-DFT
Originally posted 5 November 2026 by the employer.
About the role
This role is responsible for architecting, leading, and implementing DFT and test methodology on complex mixed-signal SOCs across multiple product generations. The work supports the Optical DSP (ODSP) team in developing chips in TSMC advanced process nodes for multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers.
What you'll do
- Define Design-for-Test (DFT) architecture and implement DFT/DFX features for custom and compute designs and IPs.
- Execute DFT validation, IP-DFT, STA, pattern generation, and post-silicon bringup and debug.
- Mentor, guide, and drive a team of DFT engineers to scale execution across multiple designs.
- Define and enhance DFT methodologies and tools to benchmark capabilities and enable new test approaches.
What you'll need
- Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 15+ years of experience, or a Master’s/PhD with 13+ years of experience.
- Hands-on experience across DFT execution stages including SCAN, MBIST, validation, STA, IP-DFX, and post-silicon bringup and debug.
- Demonstrated involvement in DFT architecture definition for at least two designs.
- Strong fundamentals in digital circuit design and logic design.
- Experience with DFT flows, methodologies, and EDA toolsets across Cadence, Mentor, and Synopsys (Genus, Modus, NCSim, DC, Tessent, Spyglass, Tmax).
Nice to have
- Prior experience in ASIC design.
- Scripting skills using Python, PERL, Tcl, and C-Shell.
More semiconductor jobs: Marvell Technology jobs · DFT engineer jobs · Santa Clara jobs
This role has been open 0 days — well below the 55-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
279
|
Median days open
55 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (279 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 279 |
| Open roles in the wider Digital Design & Verification family | 41 | 3488 · 119 employers |
| Median days open | 8 d | 55 d (−47 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 37 open roles · median 54 d
- NVIDIA · 23 open roles · median 54 d
- Qualcomm · 22 open roles · median 84 d
- Broadcom · 21 open roles · median 2 d
- NXP Semiconductors · 20 open roles · median 54 d
- Synopsys · 19 open roles · median 34 d
How we counted: 279 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.