Senior Principal Engineer- Design Verification - Bengaluru, India
Originally posted 28 September 2026 by the employer.
Join the Memory Interface Division (MID) team to drive verification for UA Link Switch products.
About the role
This role involves leading the verification strategy and execution for UA Link Switch products within the Memory Interface Division (MID). The position focuses on ensuring first-silicon success for high-performance, high-bandwidth interconnect and switching solutions.
What you'll do
- Define and own the verification strategy, methodology, and execution plan for UA Link Switch products.
- Lead verification architecture, testbench development, coverage planning, and verification closure activities.
- Build and drive scalable UVM/ System Verilog-based verification environments for complex SoC and subsystem designs.
- Collaborate with architecture, design, firmware, system validation, and silicon bring-up teams.
- Develop verification plans covering functionality, performance, reliability, error handling, and corner-case scenarios.
- Drive debug and root-cause analysis of design and verification issues.
What you'll need
- 18+ years of experience in ASIC/SoC verification.
- Proven leadership experience delivering complex SoC or subsystem verification programs.
- Strong expertise in System Verilog, UVM, Assertion-Based Verification (SVA).
- Experience with Functional and Code Coverage Methodologies, Simulation and Regression Infrastructure, and Verification Closure Techniques.
- Experience verifying large-scale digital systems involving high-speed digital designs, SoCs, subsystem integration, switching fabrics, interconnect architectures, memory controllers, memory subsystems, and microcontroller-based systems.
- Strong understanding of RTL design concepts and hardware architecture.
Nice to have
- Prior verification experience in high-speed SerDes-based systems, switching fabrics, packet-based architectures, memory interface technologies, or AI/HPC interconnect solutions.
- Experience with PCIe, CXL, Ethernet, UALink, or UCIe protocols.
- Experience with formal verification, emulation, and FPGA prototyping.
- Familiarity with performance verification and system-level validation methodologies.
- Experience debugging silicon issues and supporting post-silicon validation.
- Hands-on experience with mixed hardware/firmware verification environments.
- Experience leading geographically distributed verification teams.
This role has been open 0 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1157
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1157 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 1157 |
| Open roles in the wider Digital Design & Verification family | 84 | 3079 · 114 employers |
| Median days open | 29 d | 63 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Who's hiring in this category
- AMD · 101 open roles · median 38 d
- Qualcomm · 97 open roles · median 52 d
- NVIDIA · 85 open roles · median 70 d
- Synopsys · 65 open roles · median 23 d
- SiFive · 56 open roles · median 55 d
- NXP Semiconductors · 51 open roles · median 81 d
How we counted: 1157 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.