$200,000 - $250,000 USD yearly
Lead digital architecture and RTL for USB connectivity bridges, PCIe-to-USB host bridges, and multi-core Arm subsystems.
About the role
MaxLinear is seeking a Senior Principal Digital SoC Design Engineer to join the Analog Mixed Signal (AMS) group and lead digital architecture and RTL for connectivity bridges and embedded-processor SoCs. The role focuses on products ranging from USB-based connectivity bridges and PCIe-to-USB host bridge devices to embedded-processor SoCs for data center platform management.
What you'll do
- Lead digital architecture and RTL for USB device-side connectivity bridges, including multi-port serial (UART), I²C/SPI/GPIO bridging, endpoint/FIFO architecture, flow control, and OTP-based configurability.
- Architect and integrate PCIe-to-USB host bridge solutions, including PCIe endpoint and USB host controller (xHCI) integration, DMA engines, buffer management, interrupt and power-state handling, and register architecture.
- Define and lead digital architecture for embedded-processor SoCs for data center platform management, including multi-core Arm subsystems, memory controllers, high-speed host interfaces, and peripheral I/O.
- Drive platform security and management features, including secure boot, hardware root of trust, cryptographic checksum generator/checker, and host-to-management communication paths.
- Define on-chip interconnect, clock/reset, low-power, and DFT architecture, owning RTL quality through lint, CDC/RDC, synthesis, and timing constraints.
- Set verification strategy with the DV team—including compliance, emulation/FPGA prototyping, and firmware/driver co-verification—and partner across teams through silicon bring-up and qualification.
What you'll need
- Deep hands-on expertise in SystemVerilog/Verilog RTL design, SoC micro-architecture, and complex top-level integration.
- Strong working knowledge of USB 2.0/3.x device and host architectures (including xHCI) and PCIe endpoint architecture, with experience integrating licensed controller and PHY IP.
- Experience with serial and peripheral interfaces (UART, I²C/I3C, SPI, GPIO), bridge-type data paths, FIFOs, and DMA.
- Experience integrating embedded Arm processor subsystems, DDR/memory controllers, bus fabrics (AMBA AXI/AHB/APB), and security IP.
- Strong understanding of clock/reset, CDC/RDC, low-power design, timing constraints, synthesis, DFT, and physical design trade-offs.
- Track record delivering multiple SoCs from architecture through tapeout, silicon bring up, compliance certification, and high-volume production.
- BS in Electrical Engineering or related with 15+ years of experience, MS with 12+ years of experience, or Ph.D. with 9+ years of experience.
Nice to have
- Familiarity with data center server management concepts (e.g., eSPI, I3C, MCTP, hardware root of trust).
Skills: SystemVerilog, RTL, USB, PCIe, SoC micro-architecture, Arm subsystems
More semiconductor jobs: RTL design jobs
First seen in our index 3 days ago, well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days since first seen
66 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MaxLinear | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1070 |
| Open roles in the wider Digital Design & Verification family | 2 | 3617 · 122 employers |
| Median days since first seen | 10 d | 66 d (+56 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: SystemVerilog, RTL, USB, PCIe, SoC micro-architecture, Arm subsystems
Who's hiring in this category
- Qualcomm · 147 open roles · median 75 d
- AMD · 92 open roles · median 58 d
- Synopsys · 86 open roles · median 53 d
- NVIDIA · 48 open roles · median 70 d
- NXP Semiconductors · 43 open roles · median 108 d
- Analog Devices · 36 open roles · median 63 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.