Senior Principal Digital IC Design Engineer - Santa Clara, CA, United States
$182,360 - $273,200 USD yearly
Originally posted 27 May 2026 by the employer.
Design micro-architecture and RTL for high-speed interconnect ICs powering AI clusters in hyperscaler data centers.
About the role
As a member of the Data Center Engineering business group, you will own the digital design of high-performance mixed-signal ICs used in high-speed interconnects in hyperscaler data centers. These chips implement digital signal processing algorithms and protocol processing for interconnects in AI clusters.
What you'll do
- Design, develop, implement, verify, and document micro-architecture and RTL for power management integrated circuits. - Collaborate with system and chip architects to produce comprehensive block micro-architecture and register specifications. - Drive the full design development cycle from micro-architecture documentation and RTL coding to timing specifications, test plan reviews, and silicon bring-up in the lab. - Supervise or mentor other digital design engineers while scheduling reviews with cross-functional teams to improve design and verification methodologies.
What you'll need
- Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 12+ years of experience, a Master’s degree with 10+ years, or a PhD with 5+ years. - Extensive experience in Verilog/SystemVerilog, synthesis, STA, low power design, Spyglass, and RTL quality checks for LINT and CDC. - Hands-on scripting experience in Perl or Python. - Proven track record of delivering production-quality designs on aggressive development schedules.
Nice to have
- Domain expertise in 802.3 standards and SerDes design. - Hands-on background in digital signal processing, error correction codes, and physical layer protocols.
Skills: RTL, Verilog, SystemVerilog, Synthesis, STA, low power design
This role has been open 149 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 1084 |
| Open roles in the wider Digital Design & Verification family | 36 | 3328 · 115 employers |
| Median days open | 35 d | 63 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL, Verilog, SystemVerilog, Synthesis, STA, low power design
Who's hiring in this category
- Qualcomm · 160 open roles · median 60 d
- Synopsys · 87 open roles · median 36 d
- AMD · 77 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 92 d
- NVIDIA · 39 open roles · median 64 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.