Senior Principal Digital Design Engineer - San Jose, United States
$154,000 - $286,000 USD yearly
Originally posted 26 August 2026 by the employer.
Design, develop, and support system-level memory IP models across various memory technologies and interfaces.
About the role
As a Senior Principal Digital Design Engineer, you will be responsible for the design, development, and ongoing support of system-level memory IP models used in hardware-based verification products. This includes working across a broad range of memory technologies and interfaces such as LPDDR, HBM, NAND Flash, eMMC, SD Card, DFI, and UFS.
What you'll do
- Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms.
- Develop memory models supporting technologies and interfaces such as LPDDR, HBM, NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS.
- Maintain, enhance, debug, and support existing memory IP products throughout their lifecycle.
- Develop high-quality RTL using Verilog/SystemVerilog, applying sound design and coding practices.
- Develop and execute verification strategies using industry-standard simulation and emulation tools and methodologies.
- Diagnose and resolve complex RTL, protocol, system, and customer issues through effective debugging and root-cause analysis.
What you'll need
- MSEE or equivalent advanced degree with a minimum of 5 years of significant experience designing complex protocols, RTL, and/or hardware systems.
- Extensive hands-on experience with Verilog/SystemVerilog RTL design.
- Strong understanding of RTL verification methodologies, tools, and flows.
- Demonstrated ability to debug complex hardware, RTL, protocol, and system-level issues.
- Strong analytical and problem-solving skills, with the ability to identify root causes and develop practical solutions.
- Proven ability to work effectively as an individual contributor while collaborating closely with engineering, product, and customer-facing teams.
Nice to have
- Experience with Cadence simulation and/or emulation products.
- Experience with hardware emulation, simulation, or other hardware-based verification platforms.
- Programming or scripting experience with Perl, Tcl/Tk, C-shell, or similar languages.
- Experience with memory subsystem architecture, design, and operation.
- Experience designing or verifying memory protocols such as LPDDR, HBM, NAND Flash, eMMC, SD, DFI, or UFS.
- Experience developing reusable IP models or verification components for complex SoC or system-level environments.
Skills: system-level memory IP models, LPDDR, HBM, NAND Flash, RTL design and verification, simulation and emulation tools, debugging complex hardware
This role has been open 50 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1192 |
| Open roles in the wider Digital Design & Verification family | 122 | 3183 · 115 employers |
| Median days open | 114 d | 65 d (+49 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: system-level memory IP models, LPDDR, HBM, NAND Flash, RTL design and verification, simulation and emulation tools, debugging complex hardware
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems (this employer) · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.