Senior Principal Design Engineer-Palladium & Protium Customer Enablement & Solutions - San Jose, United States
$154,000 - $286,000 USD yearly
Originally posted 28 July 2026 by the employer.
Work with Palladium and Protium platforms to develop advanced protocol solutions.
About the role
This role involves working with industry semiconductor and systems companies to develop and deploy Cadence’s hardware emulation and FPGA prototyping platforms.
What you'll do
- Collaborate with engineering teams and customers to develop, deploy, and optimize advanced protocol solutions on Palladium and Protium platforms.
- Define and develop customer-specific emulation and prototyping requirements, focusing on high-speed interfaces and memory protocols like PCIe and CXL.
- Drive the development of advanced acceleration FW + FPGA system solutions and establish robust verification methodologies.
- Triage and resolve complex, systemic issues across the hardware/software boundary, optimizing driver behavior, protocol compliance, and system stability.
- Lead technical evaluations and develop high-performance benchmarks to demonstrate the advantages of Cadence hardware platforms.
- Create and deliver technical presentations, white papers, and product demonstrations for customers.
What you'll need
- BS with a minimum of 10 years of experience or MS with a minimum of 7 years of experience.
- Strong fundamentals in digital design, computer architecture, and system-level verification.
- Deep technical knowledge in Simulation (Advanced Testbench), Emulation (TBA & ICE), and FPGA Prototyping.
- Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++.
- Understanding of standard interconnect or IO protocols used in modern chip designs.
- Good debugging skills using waveforms, logs, and protocol analyzers.
- Ability to work across hardware and software boundaries.
Skills: hardware emulation, FPGA prototyping, Palladium, Protium, SystemVerilog
This role has been open 82 days — slightly above the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
672
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (672 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 672 |
| Open roles in the wider Physical Implementation family | 175 | 1441 · 110 employers |
| Median days open | 171 d | 73 d (+98 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: hardware emulation, FPGA prototyping, Palladium, Protium, SystemVerilog
Who's hiring in this category
- Cadence Design Systems (this employer) · 153 open roles · median 170 d
- Synopsys · 63 open roles · median 36 d
- Micron Technology · 44 open roles · median 47 d
- Qualcomm · 36 open roles · median 75 d
- GlobalFoundries · 33 open roles · median 38 d
- Keysight Technologies · 32 open roles · median 72 d
How we counted: 672 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.