Senior Principal ASIC Design Engineer - Germany (Onsite), Germany
Digital Design & SoC Architecture
Originally posted 2 August 2026 by the employer — open 39 days.
About the role
This role involves driving ASIC design for Ethernet and Scale-Up (ESUN) connectivity products within rack-scale AI infrastructure.
What you'll do
- Define and drive ASIC architecture for Ethernet/ESUN connectivity products across UALink, UCIe, PCIe Gen 6/7, and Ethernet.
- Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics.
- Define scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control.
- Lead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and AI networking subsystems.
- Design packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces.
- Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 12+ years of ASIC/SoC design experience with complex, high-speed networking or connectivity silicon.
- Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.
- Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.
- Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.
- Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation.
Nice to have
- Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols.
- Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines.
- Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems.
- Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts.
Skills: ASIC design, RTL design, Ethernet, PCIe Gen 6/7, UCIe, AI interconnect fabrics