Senior Power Integrity Co-Design Engineer - CA, Santa Clara, United States
$136,000 - $264,500 USD yearly
Originally posted 27 July 2026 by the employer.
About the role
The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform.
What you'll do
- Architect voltage-noise mitigation across the full stack—silicon, package, board, platform—and own the co-design trade-offs between them. - Co-design noise features with Speed, Power, Reliability, Circuit Design, Power-Arch, ASIC, and platform teams. - Define product-level voltage noise targets, drive them to closure, and sign them off at shipment. - Build and take ownership of the Sim-to-Si correlation methodology for noise. - Model and prototype noise features including transient sense, droop response, and mitigation IP. - Lead show-stopper noise bugs during silicon bringup. - Drive architecture-level co-design tradeoffs across V/F, Power, Noise, Reliability, and Thermal boundaries.
What you'll need
- BS, MS, or PhD in EE, CE, or related field (or equivalent experience). - 5+ years of experience in silicon power integrity, voltage noise, or PDN. - Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, or voltage regulator response. - Hands-on silicon experience with bringup, characterization, correlation, bench instrumentation (scopes, probes, DAQ), and simulators. - Strong Sim-to-Si correlation capabilities. - Demonstrated rigor in spec lock, sign-off, and OPP closure.
Skills: power integrity, di/dt mitigation, silicon, package, board
This role has been open 119 days — well above the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
479
|
Median days open
76 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (479 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 53 | 479 |
| Open roles in the wider Digital Design & Verification family | 227 | 3298 · 115 employers |
| Median days open | 71 d | 76 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: power integrity, di/dt mitigation, silicon, package, board
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA (this employer) · 54 open roles · median 71 d
- Apple · 38 open roles · median 14 d
- AMD · 35 open roles · median 71 d
- Arm Holdings · 27 open roles · median 119 d
- Micron Technology · 22 open roles · median 111 d
How we counted: 479 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.