Senior Power and Performance Engineer - Shanghai, China
Originally posted 22 October 2026 by the employer. Relisted by the employer on 22 October 2026.
Architect and integrate system-level performance and power management features within the Silicon Co-design Group.
About the role
This role is responsible for architecting and integrating system-level performance and power management features, controllers, and policies across datacenter and client products. The position resides within the ArchDev team inside the Silicon Co-design Group (SCG), spanning product development from architecture definition through silicon bringup to release.
What you'll do
- Architect and integrate system-level performance and power management features, controllers, and policies across datacenter and client products.
- Build feature roadmaps for low-power, low-noise, and performance-per-watt needs through prototyping, use-case analysis, and cost/benefit trade-offs.
- Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to guide design decisions and debug complex issues.
- Lead debug efforts, develop workarounds, and support bringup, validation, manufacturing, and customer escalations.
- Utilize AI-driven techniques, including machine learning algorithms, to enhance performance prediction models and power management strategies.
What you'll need
- BS or MS in EE/CE (or equivalent experience).
- 8+ years of experience focused on performance and power management optimizing power for perf-per-watt efficiency in datacenter or client systems, specifically covering DVFS, power gating, clock policy, sequencing, throttling, control systems, or boot/reset.
- Strong EE fundamentals in digital design, low power design, DVFS, control systems, power management techniques, timing, and architecture.
- Knowledge of PVT dependencies, binning methodologies, and VF characterization.
- Solid understanding of firmware/driver structures and HW/SW interaction with different IPs, including impact on power, latency, and reliability.
- Programming proficiency in C/C++, Python, or Perl in Windows/Linux environments.
Nice to have
- Hands-on lab experience with oscilloscopes, multimeters, and logic analyzers, as well as silicon bringup exposure.
- Published research or patents in power management or related fields.
- Experience with modeling and simulation tools for performance validation at scale and familiarity with advancements in AI applications for power and performance optimization.
- Contributions to open-source projects or communities in low-power design methodologies.
Skills: system-level performance, power management features, DVFS, power gating, clock policy, control systems
More semiconductor jobs: Power electronics jobs · China jobs
This role has been open 148 days — well above the 96-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
69
|
Median days open
96 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (69 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 69 |
| Open roles in the wider Analog & Mixed-Signal family | 26 | 1550 · 107 employers |
| Median days open | 188 d | 96 d (+92 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: system-level performance, power management features, DVFS, power gating, clock policy, control systems
Who's hiring in this category
- Renesas Electronics · 14 open roles · median 102 d
- Qualcomm · 8 open roles · median 77 d
- Infineon Technologies · 7 open roles · median 71 d
- Analog Devices · 5 open roles · median 97 d
- Monolithic Power Systems · 5 open roles · median 223 d
- AMD · 4 open roles · median 88 d
How we counted: 69 open Power Electronics (Power Management) roles from 22 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.